Figure 20. Offset Error vs Common Mode Voltage (V
參數(shù)資料
型號(hào)： LTC2435IGN#TR
廠商： Linear Technology
文件頁數(shù)： 22/42頁
文件大?。?/td> 0K
描述： IC CONV A/D 20BIT DIFF 16-SSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 20
采樣率（每秒）： 15
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，雙極
LTC2435/LTC2435-1
29
24351fc
For more information www.linear.com/LTC2435
Figure 20. Offset Error vs Common Mode Voltage (VINCM = VIN+ = VIN–)
and Input Source Resistance Imbalance (RIN = RSOURCEIN+ – RSOURCEIN–)
for Large CIN Values (CIN ≥ 1F)
A
B
C
D
E
F
G
VINCM (V)
0
OFFSET
ERROR
(ppm)
–310
–320
–330
–340
–350
–360
–370
–380
2435 F20
2.0
5.0
1.0
3.0
4.0
0.5
2.5
1.5
3.5
4.5
VCC = 5V
VREF+ = 5V
VREF– = GND
VIN+ = VIN– = VINCM
A:
RIN = 1k
B:
RIN = 500
C:
RIN = 200
D:
RIN = 0
E:
RIN = –200
F:
RIN = –500
G:
RIN = –1k
FO = GND
TA = 25°C
CIN = 10F
applicaTions inForMaTion
input signal of 0.15 10–6 fEOSCppm. Figure 20 shows
the typical offset error due to input common mode voltage
for various values of source resistance imbalance between
the IN+ and IN– pins when large CIN values are used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
Themagnitudeofthedynamicinputcurrentdependsupon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock.Whenrelativelystableresistors(50ppm/°C)areused
for the external source impedance seen by IN+ and IN–,
the expected drift of the dynamic current, offset and gain
errors will be insignificant (about 1% of their respective
valuesovertheentiretemperatureandvoltagerange).Even
for the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 100Ω source resistance will create
a 0.1V typical and 1V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2435/LTC2435-1 sample the
differentialreferencepinsREF+andREF–transferringsmall
amount of charge to and from the external driving circuits
thus producing a dynamic reference current. This current
does not change the converter offset, but it may degrade
the gain and INL performance. The effect of this current
can be analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors(CREF<0.01F),thevoltageonthesamplingcapacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01F) may
be required as reference filters in certain configurations.
Suchcapacitorswillaveragethereferencesamplingcharge
and the external source resistance will see a quasi con-
stant reference differential impedance. For the LTC2435,
when FO = LOW (internal oscillator and 60Hz notch), the
typical differential reference resistance is 15.6MΩ which
will generate a +FS gain error of approximately 0.032ppm
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