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參數(shù)資料
| 型號： | LTC2435IGN#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/42頁 |
| 文件大小： | 0K |
| 描述： | IC CONV A/D 20BIT DIFF 16-SSOP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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LTC2435/LTC2435-1
23
24351fc
For more information www.linear.com/LTC2435
applicaTions inForMaTion
24th rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result on the 24th rising edge of SCK. After
the 24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 24th rising edge of
SCK, see Figure 12. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
beavoidedbyaddinganexternal10kpull-upresistortothe
SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2435/LTC2435-1 internal
pull-up at pin SCK is disabled. Normally, SCK is not exter-
nallydrivenifthedeviceisintheinternalSCKtimingmode.
However,certainapplicationsmayrequireanexternaldriver
on SCK. If this driver goes Hi-Z after outputting a LOW
signal, the LTC2435/LTC2435-1 internal pull-up remains
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK
timing mode. By adding an external 10k pull-up resistor
to SCK, this pin goes HIGH once the external driver goes
Hi-Z. On the next CS falling edge, the device will remain
in the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
Figure 12. Internal Serial Clock, Reduced Data Output Length
SDO
SCK
(INTERNAL)
CS
>tEOCtest
MSB
SIG
BIT 8
TEST EOC
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
EOC
BIT 23
EOC
BIT 0
SLEEP
DATA OUTPUT
Hi-Z
DATA OUTPUT
CONVERSION
SLEEP
2435 F12
<tEOCtest
VCC
10k
TEST EOC
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
3-WIRE
SPI INTERFACE
1
F
2.7V TO 5.5V
LTC2435/
LTC2435-1
= 50Hz REJECTION (LTC2435)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
VCC
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