For more information www.linear.com/LTC2262-14 Phase Shifting the Output Clock I" />
參數(shù)資料
型號(hào)： LTC2262CUJ-14#TRPBF
廠(chǎng)商： Linear Technology
文件頁(yè)數(shù)： 11/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT 150MSPS 40-QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 14
采樣率（每秒）： 150M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 171mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 40-QFN（6x6）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分
配用： DC890B-ND - BOARD USB DATA COLLECTION
19
226214fc
LTC2262-14
For more information www.linear.com/LTC2262-14
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
setup-and-hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2262-14 can also phase shift the CLKOUT+/
CLKOUT– signals by serially programming mode con-
trol register A2. The output clock can be shifted by
0°, 45°, 90° or 135°. To use the phase shifting feature
the clock duty cycle stabilizer must be turned on.
Another control register bit can invert the polarity of
CLKOUT+ and CLKOUT–, independently of the phase shift.
The combination of these two features enables phase
shifts of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>1.000000V
+0.999878V
+0.999756V
1
0
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1110
+0.000122V
+0.000000V
–0.000122V
–0.000244V
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–0.999878V
–1.000000V
≤–1.000000V
0
1
00 0000 0000 0001
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is “randomized” by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is ap-
plied—an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output randomizer is enabled by
serially programming mode control register A4.
Alternate Bit Polarity
Another feature that reduces digital feedback on the circuit
board is the alternate bit polarity mode. When this mode
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11,
D13) are inverted before the output buffers. The even bits
(D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are not
affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
When there is a very small signal at the input of the A/D
thatiscenteredaroundmidscale,thedigitaloutputstoggle
between mostly 1s and mostly 0s. This simultaneous
APPLICATIONS INFORMATION
Figure 14. Phase Shifting CLKOUT
CLKOUT+
D0-D13, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
1
CLKPHASE1
MODE CONTROL BITS
0
1
0
1
CLKPHASE0
0
1
0
1
0
1
0
1
226214 F14
ENC+
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LTC2262IUJ-12#PBF 功能描述:IC ADC 12BIT 150MSPS 40-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類(lèi)型:1 個(gè)單端，雙極
LTC2262IUJ-12#TRPBF 功能描述:IC ADC 12BIT 150MSPS 40-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類(lèi)型:1 個(gè)單端，雙極
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LTC2262IUJ-14#TRPBF 制造商:Linear Technology 功能描述:ADC Single Pipelined 150Msps 14-bit Parallel/LVDS 40-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 14BIT 150MSPS 40-QFN
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