參數(shù)資料
型號(hào): LTC2153IUJ-14#PBF
廠商: Linear Technology
文件頁數(shù): 5/24頁
文件大?。?/td> 0K
描述: IC ADC 14BIT DUAL 310MSPS 40QFN
標(biāo)準(zhǔn)包裝: 61
位數(shù): 14
采樣率(每秒): 310M
數(shù)據(jù)接口: 并聯(lián),串行,SPI
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 479mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-QFN(6x6)
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)差分
配用: DC1371A-ND - BOARD USB DATA ACQUISITION HS
13
215314f
LTC2153-14
applicaTions inForMaTion
coupling capacitors are needed (Figures 9 and 10). The
maximum (peak) voltage of the input signal should never
exceed VDD +0.1V or go below –0.1V.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintainaconstant50%internaldutycycle.Thedutycycle
stabilizer is enabled via SPI Register A2 (see Table 3) or
by CS in parallel programming mode.
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. In
Figure 9. Sinusoidal Encode Drive
this case, care should be taken to make the clock a 50%
(±5%) duty cycle.
DIGITAL OUTPUTS
The digital outputs are double-data rate LVDS signals.
Two data bits are multiplexed and output on each differ-
ential output pair. There are seven LVDS output pairs
(D0_1+/D0_1through D12_13/D12_13+). Overflow
(OF+/OF) and the data output clock (CLKOUT+/CLKOUT)
each have an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode
voltage.
LTC2153-14
VDD
215314 F09
1.2V
10k
50
100
50
0.1F
T1: MACOM
ETC1-1-13
Figure 10. PECL or LVDS Encode Drive
VDD
LTC2153-14
PECL OR
LVDS INPUT
215314 F10
1.2V
10k
100
0.1F
ENC+
ENC
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