LTC2153-14: IVDD
參數(shù)資料
型號: LTC2153IUJ-14#PBF
廠商: Linear Technology
文件頁數(shù): 23/24頁
文件大?。?/td> 0K
描述: IC ADC 14BIT DUAL 310MSPS 40QFN
標(biāo)準(zhǔn)包裝: 61
位數(shù): 14
采樣率(每秒): 310M
數(shù)據(jù)接口: 并聯(lián),串行,SPI
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 479mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-QFN(6x6)
包裝: 管件
輸入數(shù)目和類型: 1 個差分
配用: DC1371A-ND - BOARD USB DATA ACQUISITION HS
LTC2153-14
8
215314f
Typical perForMance characTerisTics
LTC2153-14: Frequency Response
LTC2153-14: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
SAMPLE RATE (Msps)
130
I VDD
(mA)
150
160
170
62
186
248
140
200
190
180
0
124
310
215314 G19
1000
100
INPUT FREQUENCY (MHz)
INPUT
AMPLITUDE
(dBFS)
–4.0
–1.5
–1.0
–0.5
–2.5
–4.5
–2.0
–3.0
–3.5
215314 G20
LTC2153-14: IOVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
SAMPLE RATE (Msps)
I OVDD
(mA)
35
45
55
50
150
200
250
25
60
30
40
50
20
0
100
300
215314 G18
LVDS CURRENT
3.5mA
LVDS CURRENT
1.75mA
pin FuncTions
VDD (Pins 1, 2): 1.8V Analog Power Supply. Bypass to
ground with 0.1F ceramic capacitor. Pins 1, 2 can share
a bypass capacitor.
GND (Pins 3, 6, 10, 13, 35, Exposed Pad Pin 41): ADC
Power Ground. The exposed pad must be soldered to the
PCB ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN– (Pin 5): Negative Differential Analog Input.
SENSE (Pin 7): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±0.66V
input range. An external reference between 1.23V and
1.27V applied to SENSE selects an input range of ±0.528
VSENSE.
VREF (Pin 8): Reference Voltage Output. Bypass to ground
with a 2.2F ceramic capacitor. Nominally 1.25V.
VCM (Pin 9): Common Mode Bias Output; nominally equal
to 0.439 VDD. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1F
ceramic capacitor.
ENC+ (Pin 11): Encode Input. Conversion starts on the
rising edge.
ENC(Pin 12): Encode Complement Input. Conversion
starts on the falling edge.
OVDD (Pins 20, 30): 1.8V Output Driver Supply. Bypass
to ground with a 0.1F ceramic capacitor.
OGND (Pin 21): LVDS Driver Ground.
SDO (Pin 36): Serial Interface Data Output. In serial pro-
grammingmode,(PAR/SER=0V),SDOistheoptionalserial
interface data output. Data on SDO is read back from the
mode control registers and can be latched on the falling
edge of SCK. SDO is an open-drain N-channel MOSFET
output that requires an external 2k pull-up resistor from
1.8V to 3.3V. If readback from the mode control registers
is not needed, the pull-up resistor is not necessary and
SDO can be left unconnected.
SDI(Pin37):SerialInterfaceDataInput.Inserialprogram-
ming mode, (PAR/SER = 0V), SDI is the serial interface
data input. Data on SDI is clocked into the mode control
registersontherisingedgeofSCK.Inparallelprogramming
mode (PAR/SER = VDD), SDI selects 3.5mA or 1.75mA
LVDS output current (see Table 2).
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