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參數(shù)資料
| 型號(hào)： | LTC1704EGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 347K |
| 描述： | IC REG DL BUCK/LINEAR 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 拓?fù)洌?/td> | 降壓（降壓）（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 550kHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 控制器 |
| 帶 LED 驅(qū)動(dòng)器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 3.15 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
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LTC1704/LTC1704B
16
1704bfa
APPLICATIO S I FOR ATIO
U
U
U
Maximizing High Load Current Efficiency
Efficiency at high load currents is primarily controlled by
the resistance of the components in the power path (QT,
QB, L) and power lost in the gate drive circuits due to
MOSFET gate charge. Maximizing efficiency in this region
of operation is as simple as minimizing these terms.
The behavior of the load over time affects the efficiency
strategy. Parasitic resistances in the MOSFETs and the
inductor set the maximum output current the circuit can
supply without burning up. A typical efficiency curve
shows that peak efficiency occurs near 30% of this maxi-
mum current. If the load current will vary around the
efficiency peak and spend relatively little time at the
maximum load, choosing components so that the average
load is at the efficiency peak is a good idea. This puts the
maximum load well beyond the efficiency peak, but usu-
ally gives the greatest system efficiency over time, which
translates to the longest run time in a battery-powered
system. If the load is expected to be relatively constant at
the maximum level, the components should be chosen so
that this load lands at the peak efficiency point, well below
the maximum possible output of the converter.
Maximizing Low Load Current Efficiency
Low load current efficiency depends strongly on proper
operation in Burst Mode operation. In an ideally optimized
system, when Burst Mode operation is activated, gate
drive is the dominant loss term. Burst Mode operation
turns off all output switching for several clock cycles in a
row, significantly cutting gate drive losses. As the load
current in Burst Mode operation falls toward zero, the
current drawn by the circuit falls to the LTC1704s back-
ground quiescent level, about 4.5mA.
To maximize low load efficiency, make sure the LTC1704
(non-B part) is allowed to enter Burst Mode operation as
cleanly as possible. Minimize ringing at the SW node so
that the Burst comparator leaves as little residual current
in the inductor as possible when QB turns off. It helps to
connect the SW pin of the LTC1704 as close to the drain
of QB as possible. An RC snubber network can also be
added from SW to PGND.
SWITCHER SUPPLY EXTERNAL
COMPONENT SELECTION
Power MOSFETs Selection
Getting peak efficiency out of the LTC1704 switcher sup-
ply depends strongly on the external MOSFETs used. The
LTC1704 requires at least two external MOSFETsmore
if one or more of the MOSFETs are paralleled to lower on-
resistance. To work efficiently, these MOSFETs must
exhibit low R
DS(ON)
at 5V V
GS
to minimize resistive power
loss while they are conducting current. They must also
have low gate charge to minimize transition losses during
switching. On the other hand, voltage breakdown require-
ments in a typical LTC1704 circuit are pretty tame; the 6V
maximum input voltage limits the V
DS
and V
GS
the MOSFETs
can see to safe levels for most devices.
Low R
DS(ON)
R
DS(ON)
calculations are pretty straightforward. R
DS(ON)
is
the resistance from the drain to the source of the MOSFET
when the gate is fully on. Many MOSFETs have R
DS(ON)
specified at 4.5V gate drivethis is the right number to
use in LTC1704 circuits running from a 5V supply. As
current flows through this resistance while the MOSFET is
on, it generates I
2
R watts of heat, where I is the current
flowing (usually equal to the output current) and R is the
MOSFET R
DS(ON)
. This heat is only generated when the
MOSFET is on. When it is off, the current is zero and the
power lost is also zero (and the other MOSFET is busy
losing power).
This lost power does two things: it subtracts from the
power available at the output, costing efficiency, and it
makes the MOSFET hotter, both bad things. The effect is
worst at maximum load when the current in the MOSFETs
and thus the power lost, are at a maximum. Lowering
R
DS(ON)
improves heavy load efficiency at the expense of
additional gate charge (usually) and more cost (usually).
Proper choice of MOSFET R
DS(ON)
becomes a trade-off
between tolerable efficiency loss, power dissipation and
cost. Note that while the lost power has a significant effect
on system efficiency, it only adds up to a watt or two in a
typical LTC1704 circuit, allowing the use of small, surface
mount MOSFETs without heat sinks.
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