參數(shù)資料
型號(hào)： LTC1421ISW-2.5#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 8/24頁(yè)
文件大?。?/td> 329K
描述： IC CONTROLLER HOT SWAP 24-SOIC
標(biāo)準(zhǔn)包裝： 32
類(lèi)型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開(kāi)關(guān)： 無(wú)
電源電壓： 3 V ~ 12 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC
包裝： 管件
8
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
U
U
U
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the board can draw huge
transient currents from the backplane power bus as they
charge up. The transient currents can cause permanent
damage to the connector pins and cause glitches on the
system supply, causing other boards in the system to
reset. At the same time, the system data bus can be
disrupted when the boards data pins make or break
connection.
The LTC1421 is designed to turn a boards supply voltages
on and off in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
also provides a disable signal for the boards data bus
buffer during insertion or removal and provides all the
necessary supply supervisory functions for the board.
Power Supply Ramping
The power supplies on a board are controlled by placing
external N-channel pass transistors in the power path
(Figure 3). R1 and R2 provide current fault detection. By
ramping the gate of the pass transistor up at a controlled
rate, the transient surge current (I = C " dV/dt) drawn from
the main backplane supply can be limited to a safe value
when the board makes connection.
Figure 3: Supply Control Circuitry
23
1
10
5V
12V
2
R1
Q1
22
21
20    19
18
17
16
+
R2
Q2
C
LOAD
C
LOAD
+
V
CCLO
SETLO GATELO V
OUTLO
LTC1421
1421 F03
V
CCHI
SETHI GATEHIV
OUTHI
RAMP
CON1
CON2
C
RAMP
V
OUTHI
V
OUTLO
4
3
2
1
4
3
2
1
R
RAMP
When power is first applied to the chip, the gates of both
N-channels, GATELO and GATEHI are pulled low. After the
connection sense pins, CON1 and CON2 are both held low
for at least 20ms, a 20礎(chǔ) reference current is connected
from the RAMP pin to GND. The voltage at GATEHI begins
to rise with a slope equal to 20礎(chǔ)/C
RAMP
 (Figure 4), where
C
RAMP
 is an external capacitor connected between the
Figure 4. Supplies Turning On
12V
5V
1421 F4a
t
1
t
2
V
OUTHI
V
OUTLO
SLOPE = 20礎(chǔ)/C
RAMP
12V
12V
~1m
0V
12V
5V
PON
9
B
R5
16k
5%
B
V
EE
0V
~1m
1421 F
R4
20k
5%
C2
0.047礔
C
LOAD
V
EE
12V
1A
Q3
1/2 MMDF3N0HD
12V FROM
CONNECTOR
CPON
LTC1421
Figure 5. Negative Supply Control
RAMP and GATEHI pins. The voltage at the GATEHI pin is
clamped one Schottky diode drop below GATELO.
The ramp time for each supply is equal to: t = (V
CC
)
(C
RAMP
)/20礎(chǔ). During power down the gates are actively
pulled down by two internal NFETs.
A negative supply voltage can be controlled using the
CPON pin as shown in Figure 5.
When the board makes connection, the transistor Q3 is
turned off because its gate is pulled low to 12V by R4.
CPON is also pulled to 12V. When the charge pump is
turned on, CPON is pulled to V
CCLO
 and the gate of Q3 will
ramp up with a time constant determined by R4, R5 and
C2. When the charge pump is turned off, CPON goes into
a high impedance state, the gate of Q3 is discharged to V
EE
with a time constant determined by R4 and C2, and Q3
turns off.
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