參數(shù)資料
型號: LTC1421ISW-2.5#PBF
廠商: Linear Technology
文件頁數(shù): 15/24頁
文件大?。?/td> 329K
描述: IC CONTROLLER HOT SWAP 24-SOIC
標準包裝: 32
類型: 熱交換控制器
應用: 通用
內(nèi)部開關:
電源電壓: 3 V ~ 12 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 24-SOIC
包裝: 管件
15
LTC1421/LTC1421-2.5
APPLICATIONS INFORMATION
U
U
U
time point 2). Pulses less than 20ms on POR are ignored.
CPON goes low. Both GATEHI and GATELO will be
actively pulled down to GND. When V
OUTLO
 drops below
its reset threshold voltage, PWRGD will immediately pull
low (time point 3) followed by RESET and DISABLE 32祍
later (time point 4). Both supplies will be discharged to
ground and stay there until POR is pulled high.
The circuit breaker can be reset by pulling POR low. After
POR is low for more than 20ms, the chip will immediately
try to power up the supplies once the outputs are below the
V
TRIP
 point.
Circuit Breaker Timing
The waveforms for the circuit when a short occurs on
either supply during board insertion are shown in
Figure 16. Time points 1 to 4 are the same as the board
insertion example, but at time point 5, a short circuit is
detected on one of the supplies. The charge pumps are
immediately turned off, the outputs V
OUTHI
 and V
OUTLO
 are
actively pulled to GND and the CPON and FAULT pins are
pulled low. At time point 6, the circuit breaker is reset by
pulling POR low. After POR has been low for 20ms (time
point 7), CPON and FAULT are pulled high, the 20礎
reference current is connected to RAMP and the charge
pumps are enabled. V
OUTHI
and V
OUTLO
 ramp up at a
controlled rate. When V
OUTLO
  has exceeded its reset
threshold, the PWRGD signal is pulled high (time point 8).
After a 200ms delay, RESET is pulled high and DISABLE
goes low.
Figure 16. Circuit Breaker Timing
V
CCLO
1
2
3
4
5
6
V
CCHI
DISABLE
CON1
7
8
9
CON2
CPON
PWRGD
V
TH1
1421 F16
V
OUTHI
GATEHI
GATELO
V
OUTLO
RESET
FAULT
POR
20ms
20ms
200ms
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