參數(shù)資料
型號(hào)： LTC1235CN
廠商： LINEAR TECHNOLOGY CORP
元件分類： 電源管理
英文描述： Microprocessor Supervisory Circuit
中文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP16
封裝： 0.300 INCH, PLASTIC, DIP-16
文件頁數(shù)： 4/16頁
文件大?。?/td> 295K
代理商： LTC1235CN
4
LTC1235
PARAMETER
CONDITONS
MIN
TYP
MAX
UNITS
RESET and WDO Output Voltage
(Note 6)
RESET, RESET, WDO, LOW LINE
Output Short Circuit Current (Note 6)
WDI Input Threshold
I
SINK
= 1.6mA, V
CC
= 5V
SOURCE
= 1
μ
A, V
CC
= 4.25V
Output Source Current
Output Sink Current
Logic Low
Logic High
WDI = V
OUT
WDI = 0V
0.4
V
3.5
1
3
25
μ
A
mA
25
0.8
V
2.0
WDI Input Current
G
G
4
50
μ
A
–50
–8
Power Fail Detector
PFI Input Threshold
PFI Input Threshold PSRR
PFI Input Current
PFO Output Voltage (Note 6)
V
CC
= 5V
G
1.25
1.3
0.3
±
0.01
1.35
V
mV/V
±
25
0.4
nA
V
I
SINK
= 3.2mA
I
SOURCE
= 1
μ
A
PFI = HIGH, PFO = 0V
PFI = LOW, PFO = V
OUT
V
IN
= –20mV, V
OD
= 15mV
V
IN
= 20mV, V
OD
= 15mV
with 10k
Pullup
3.5
1
PFO Short Circuit Source Current
(Note 6)
PFI Comparator Response Time (falling)
PFI Comparator Response Time (rising)
(Note 6)
Chip Enable Gating
CE IN Threshold
3
30
2
40
8
25
μ
A
mA
μ
s
μ
s
V
IL
V
IH
0.8
V
2.0
CE IN Pullup Current (Note 4)
CE OUT Output Voltage
3
μ
A
V
I
SINK
= 3.2mA
I
SOURCE
= 3.0mA
I
SOURCE
= 1
μ
A, V
CC
= 0V
V
CC
= 5V, C
L
= 20pF
0.4
V
OUT
– 1.50
V
OUT
– 0.05
CE Propagation Delay
20
20
30
35
35
45
ns
G
CE OUT Output Short Circuit Current
Output Source Current
Output Sink Current
mA
V
CC
= Full Operating Range, V
BATT
= 2.8V, Backup = No Connection, T
A
= 25
°
C, unless otherwise noted.
ELECTRICAL C
HARA TERISTICS
The
G
denotes specifications which apply over the operating temperature
range.
Note 1:
Absolute maximum ratings are those values beyond which the life
of device may be impaired.
Note 2:
All voltage values are with respect to GND.
Note 3:
For military temperature range parts, consult the factory.
Note 4:
The input pins of PB RST, BACKUP and CE IN, have weak internal
pullups which pull to the supply when the input pins are floating.
Note 5:
The LTC1235 can be programmed either to provide or not to
provide battery backup power to the V
OUT
pin during power failure. The
power down condition of V
OUT
is selected by the logic level of the BACKUP
pin which is latched internally when V
CC
falls through the reset voltage
threshold. If the latched logic level of the BACKUP pin is high, V
OUT
will be
in Battery Backup Mode and will be switched to V
BATT
when V
CC
falls
below V
BATT
. If the latched logic level of the BACKUP pin is low, V
OUT
will
be in Battery Saving Mode when V
CC
falls below V
BATT
.
Note 6:
The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and
RESET have weak internal pullups of typically 3
μ
A. However, external
pullup resistors may be used when higher speed is required.
Note 7:
The push-button reset input requires an active low signal.
Internally, this input signal is debounced and timed for a minimum of
40ms. When this condition is satisfied, the reset outputs go to the active
states. The reset outputs will remain in active states for a minimum of
140ms from the moment the push-button reset input is released from
logic low level.
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