參數(shù)資料
型號： LTC1235CN
廠商： LINEAR TECHNOLOGY CORP
元件分類： 電源管理
英文描述： Microprocessor Supervisory Circuit
中文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP16
封裝： 0.300 INCH, PLASTIC, DIP-16
文件頁數(shù)： 11/16頁
文件大小： 295K
代理商： LTC1235CN
11
LTC1235
U
S
A
O
PPLICATI
U
U
Table 1 shows the state of each pin during battery backup.
If the backup battery is not used, connect V
BATT
to GND
and V
OUT
to V
CC
.
IN and CE OUT, control the Chip Enable or Write inputs of
CMOS RAM. When V
CC
is +5V, CE OUT follows CE IN with
a typical propagation delay of 20ns. When V
CC
falls below
the reset voltage threshold or V
BATT
, CE OUT is forced
high, independent of CE IN. CE OUT is an alternative signal
to drive the CE, CS, or Write input of battery-backed up
CMOS RAM. CE OUT can also be used to drive the Store
or Write input of an EEPROM, EAROM or NOVRAM to
achieve similar protection. Figure 6 shows the timing
diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor’s address
decoder output. Figure 7 shows a typical nonvolatile
CMOS RAM application.
Figure 6. Timing Diagram for CE IN and CE OUT
SIGNAL
V
CC
BACKUP
V
OUT
V
BATT
BATT ON
PFI
PFO
PB RST
RESET
RESET
LOW LINE Logic low
WDI
WDO
CE IN
CE OUT
STATUS
C2 monitors V
CC
for active switchover.
BACKUP is ignored.
V
OUT
is connected to V
BATT
through an internal PMOS switch.
The supply current is 1
μ
A maximum.
Logic high. The open circuit output voltage is equal to V
OUT
.
Power Failure Input is ignored.
Logic low
PB RST is ignored.
Logic low
Logic high. The open circuit output voltage is equal to V
OUT
.
Watchdog Input is ignored.
Logic high. The open circuit output voltage is equal to V
OUT
.
Chip Enable Input is ignored.
Logic high. The open circuit output voltage is equal to V
OUT
.
Table 1. Input and Output Status in Battery Backup Mode
Memory Protection
The LTC1235 includes memory protection circuitry which
ensures the integrity of the data in memory by preventing
write operations when V
CC
is at invalid level. Two pins, CE
+5V
+3V
0.1μF
10μF
V
BATT
V
CC
LTC1235
V
OUT
GND
LTC1235 F06
V
CC
RESET
CE IN
CE OUT
BACKUP
0.1μF
TO μP
FROM DECODER
CS
20ns PROPAGATION DELAY
62512
RAM
+
GND
Figure 7. A Typical Nonvolatile CMOS RAM Application
V
CC
V1
CE IN
V
OUT
= V
BATT
V
OUT
= V
BATT
V2
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
LTC1235 F06
CE OUT
BACKUP = V
CC
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