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參數(shù)資料
| 型號： | LTC1235 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Microprocessor Supervisory Circuit |
| 中文描述： | 微處理器監(jiān)控電路 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 295K |
| 代理商： | LTC1235 |
6
LTC1235
PI FU
U
V
CC
:
+5V supply input. The V
CC
pin should be bypassed
with a 0.1
μ
F capacitor.
Backup:
Logic input to control the PMOS switch, M2,
when V
CC
is lower than V
BATT
. While V
CC
is falling through
the reset voltage threshold, the status of the BACKUP pin
(logic low or logic high) is latched in Memory Logic and
used to turn on or off M2 when V
CC
is below V
BATT
. If the
latched status of the BACKUP pin is high, the Memory
Logic turns on M2 when V
CC
falls to 50mV greater than
V
BATT
. If the latched status of the BACKUP pin is low, the
Memory Logic keeps M2 off even after V
CC
falls below
V
BATT
. If the BACKUP pin is left floating it will be pulled high
by an internal pullup and the LTC1235 will provide battery
backup when V
CC
falls.
V
OUT
:
Voltage output for backed up memory. Bypass with
a capacitor of 0.1
μ
F or greater. During normal operation,
V
OUT
obtains power from V
CC
through an NMOS power
switch, M1, which can deliver up to 50mA and has a typical
on resistance of 5
. When V
CC
is lower than V
BATT
, the
status of the BACKUP pin stored in Memory Logic controls
M2. If the status is high, the Memory Logic turns on M2
and V
OUT
is internally switched to V
BATT
through M2. If the
status is low, the Memory Logic keeps M2 off and V
OUT
is
in Battery Saving Mode. If V
OUT
and V
BATT
are not used,
connect V
OUT
to V
CC
.
V
BATT
:
Backup battery input. When V
CC
falls below V
BATT
,
the status of the BACKUP pin stored in the Memory Logic
controls M2. If the status is high, auxiliary power, connected
to V
BATT
is delivered to V
OUT
through M2. If the status is
low, the Memory Logic keeps M2 off and V
OUT
is in Battery
Saving Mode. If backup battery or auxiliary power is not
used, V
BATT
should be connected to GND.
GND:
Ground pin.
BATT ON:
Battery on logic output from comparator C2.
BATT ON goes low when V
OUT
is internally connected to
V
CC
. The output typically sinks 35mA and can provide base
drive for an external PNP transistor to increase the output
current above the 50mA rating of V
OUT
. BATT ON goes
high when V
CC
falls below V
BATT
, if the status of the
BACKUP pin stored in Memory Logic is high and V
OUT
is
switched to V
BATT
.
PFI:
Power Failure Input. PFI is the noninverting input to
the Power Fail Comparator, C3. The inverting input is
internally connected to a 1.3V reference. The Power Failure
Output remains high when PFI is above 1.3V and goes low
when PFI is below 1.3V. Connect PFI to GND or V
OUT
when
C3 is not used.
PFO:
Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When V
CC
is lower than V
BATT
, C3 is shut down and
PFO is forced low.
PB RST:
Logic input for direct connection to a push-
button. The push-button reset input requires an active low
signal. Internally, this input signal is debounced and timed
for a minimum of 40ms. When this condition is satisfied,
the reset pulse generator forces RESET to active low. The
RESET signal will remain active low for a minimum of
140ms from the moment the push-button reset input is
released from logic low level.
RESET:
Logic output for
μ
P reset control. The LTC1235
provides three ways to generate
μ
P reset. First, whenever
V
CC
falls below either the reset voltage threshold (4.65V,
typically) or V
BATT
, RESET goes active low. After V
CC
returns to 5V, the reset pulse generator forces RESET to
remain active low for a minimum of 140ms. Second, when
the watchdog timer is enabled but not serviced prior to the
time-out period, the reset pulse generator also forces
RESET to active low for a minimum of 140ms for every
time-out period (see Figure 11). Third, when the PB RST
pin stays active low for a minimum of 40ms, RESET is
forced low by reset pulse generator. The RESET signal will
remain active low for a minimum of 140ms from the
moment the push-button reset input is released from logic
low level.
RESET:
RESET is an active high logic output. It is the
inverse of RESET.
LOW LINE:
Logic output from comparator C1. LOW LINE
indicates a low line condition at the V
CC
input. When V
CC
falls below the reset voltage threshold (4.65V typically),
LOW LINE goes low. As soon as V
CC
rises above the reset
voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when V
CC
drops below V
BATT
(see
Table 1).
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|---|---|
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC1235CN | 功能描述:IC MPU SUPERVISORY CIRCUIT 16DIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復(fù)位:高有效 復(fù)位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應(yīng)商設(shè)備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
| LTC1235CN#PBF | 功能描述:IC MPU SUPERVISORY CIRCUIT 16DIP RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 其它有關(guān)文件:STM6905 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 類型:多壓監(jiān)控器 監(jiān)視電壓數(shù)目:5 輸出:開路漏極或開路集電極 復(fù)位:低有效 復(fù)位超時:最小為 140 ms 電壓 - 閥值:2.188V，2.955V，可調(diào)，可調(diào)，可調(diào) 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:Digi-Reel® 產(chǎn)品目錄頁面:1197 (CN2011-ZH PDF) 其它名稱:497-8728-6 |
| LTC1235CSW | 功能描述:IC MPU SUPERVISRY CIRCUIT 16SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復(fù)位:高有效 復(fù)位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應(yīng)商設(shè)備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
| LTC1235CSW#PBF | 功能描述:IC MPU SUPERVISRY CIRCUIT 16SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 其它有關(guān)文件:STM6905 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 類型:多壓監(jiān)控器 監(jiān)視電壓數(shù)目:5 輸出:開路漏極或開路集電極 復(fù)位:低有效 復(fù)位超時:最小為 140 ms 電壓 - 閥值:2.188V，2.955V，可調(diào)，可調(diào)，可調(diào) 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:Digi-Reel® 產(chǎn)品目錄頁面:1197 (CN2011-ZH PDF) 其它名稱:497-8728-6 |
| LTC1235CSW#TR | 功能描述:IC MPU SUPERVISRY CIRCUIT 16SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復(fù)位:高有效 復(fù)位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應(yīng)商設(shè)備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
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