參數(shù)資料
型號: LTC1235
廠商: Linear Technology Corporation
英文描述: Microprocessor Supervisory Circuit
中文描述: 微處理器監(jiān)控電路
文件頁數(shù): 12/16頁
文件大?。?/td> 295K
代理商: LTC1235
12
LTC1235
Choose R3 = 300k
and R1 = 51k
. Also select R4 =
10k
which is much smaller than R3.
7.5V =1.3V 1+51k
R2
R2 = 9.7k
, Choose nearest 5% resistor 10k and recalcu-
late V
L
,
51k
10k
V
HYSTERESIS
= 8.151V – 7.32V = 831mV
U
S
A
O
PPLICATI
IU
U
Power Fail Warning
The LTC1235 generates a Power Failure Output (PFO) for
early warning of failure in the microprocessor's power
supply. This is accomplished by comparing the Power
Failure Input (PFI) with an internal 1.3V reference. PFO
goes low when the voltage at PFI pin is less than 1.3V.
Typically PFI is driven by an external voltage divider (R1
and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 5V output. The voltage
divider ratio can be chosen such that the voltage at PFI pin
falls below 1.3V several milliseconds before the +5V
supply falls below the maximum reset voltage threshold
4.75V. PFO is normally used to interrupt the microproces-
sor to execute shut-down procedure between PFO and
RESET or RESET.
The power fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resis-
tor between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the
summing junction at the PFI pin.
V =1.3V 1+R1
R2
R3
When PFO output is high, the series combination of R3 and
R4 source current into the PFI summing junction.
Example 1:
The circuit in Figure 8 demonstrates the use of
the power fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supply input V
IN
is 100mV/ms and the total time to execute
a shut-down procedure is 8ms. Also the noise of V
IN
is
200mV. With these assumptions in mind, we can reason-
ably set V
L
= 7.5V which 1.25V greater than the sum of
maximum reset voltage threshold and the dropout voltage
of LT1086-5 (4.75V + 1.5V) and V
HYSTERESIS
= 850mV.
10μF
100μF
R3
300k
V
IN
V
OUT
ADJ
LTC1235 F07
V
CC
0.1μF
R4
10k
TO
μ
P
GND
PFO
PFI
LT1086-5
V
IN
7.5V
LTC1235
R1
51k
R2
10k
+
+
+5V
BACKUP
10μF
10μF
V
IN
V
OUT
ADJ
LTC1235 F08
V
CC
0.1μF
TO μP
PFO
PFI
GND
LT1086-5
V
IN
6.5V
+
R4
10k
+
R1
27k
R3
2.7M
R2
8.2k
+5V
R5
3.3k
LTC1235
BACKUP
Figure 9. Monitoring RegulatedDC Supply with the LTC1235
Power Fail Comparator
Figure 8. Monitoring UnregulatedDC Supply with the
LTC1235 Power Fail Comparator
R3
5.88 R1
R1
H
+
V
1.3V 1
R2–(5V –1.3V)R1
1.3V(R3 R4)
L
=
+
Assuming R4R3,V
5VR1
R3
HYSTERESIS
=
V
5VR1
R3
850mV
HYSTERESIS
=
=
–(5V –1.3V)51k
1.3V(310k )
V
1.3V 1
–(5V –1.3V)51k
1.3V(310k
7.32V
L
=
+
=
)
(7.32V – 6.25V)
100mV/ms
V
1.3V 1
51k
10k
51k
300k
8.151V
H
=
+
+
=
10.7ms
=
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