參數(shù)資料
型號(hào)： LT3837IFE#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 110 kHz SWITCHING FREQ-MAX, PDSO16
封裝： 4.40 MM, LEAD FREE, PLASTIC, TSSOP-16
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 247K
代理商： LT3837IFE#TRPBF
LT3837
23
3837fc
APPLICATIONS INFORMATION
OUTPUT VOLTAGE
RIPPLE WAVEFORM
SECONDARY
CURRENT
PRIMARY
CURRENT
IPRI
VCOUT
3825 F07
RINGING
DUE TO ESL
IPRI
N
VESR
Figure 7. Typical Flyback Converter Waveforms
ESR and ESL along with bulk capacitance directly affect
the output voltage ripple. The waveforms for a typical
yback converter are illustrated in Figure 7.
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose
of simplicity we will choose 2% for the maximum output
ripple, divided equally between the ESR step and the
charging/discharging ΔV. This percentage ripple changes,
depending on the requirements of the application. You can
modify the following equations.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
ESR
VDC
I
COUT
OUT
MAX
OUT
≤
()
1
%
–
The other 1% is due to the bulk C component, so use:
C
I
Vf
OUT
OSC
≥
1%
In many applications the output capacitor is created from
multiple capacitors to achieve desired voltage ripple, reli-
ability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satises the required bulk C.
Continuing our example, the output capacitor needs:
ESR
V
A
m
C
A
COUT
OUT
≤
()
=Ω
≥
1
33
1 524
10
16
10
1
%
.
–
. %
.
%
% .
3 3 200
1515
kHz
F
=μ
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
Most capacitor ripple current ratings are based on 2000
hour life. This makes it advisable to derate the capacitor
or to choose a capacitor rated at a higher temperature
than required.
One way to reduce cost and improve output ripple is to
use a simple LC lter. Figure 8 shows an example of the
lter.
RLOAD
COUT2
1μF
VOUT
COUT
470μF
C1
47μF
3
FROM
SECONDARY
WINDING
L1
0.1μH
3837 F08
Figure 8
SwitcherCAD is a trademark of Linear Technology Corporation.
The design of the lter is beyond the scope of this data
sheet. However, as a starting point, use these general
guide lines. Start with a COUT 1/4 the size of the nonlter
solution. Make C1 1/4 of COUT to make the second lter
pole independent of COUT. The smaller C1 may be best
implemented with multiple ceramic capacitors. Make L1
smaller than the output inductance of the transformer. In
general, a 0.1μH lter inductor is sufcient. Add a small
ceramic capacitor (COUT2) for high frequency noise on
VOUT. For those interested in more details refer to “Sec-
ond-Stage LC Filter Design,” Ridley, Switching Power
Magazine, July 2000, p8-10.
Circuit simulation is a way to optimize output capacitance
and lters, just make sure to include the component
parasitics. LTC SwitcherCAD is a terric free circuit
simulation tool that is available at www.linear.com. Final
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
signicantly impact ripple. Refer to the PC Board Layout
section for more details.
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