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參數(shù)資料
| 型號(hào)： | LT3751IUFD#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC20 |
| 封裝： | 4 X 5 MM, LEAD FREE, PLASTIC, QFN-20 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 403K |
| 代理商： | LT3751IUFD#TRPBF |
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LT3751
20
3751fb
APPLICATIONS INFORMATION
detected to when the gate transitions to the low state.
This delay increases the peak current limit by
(VTRANS)(180ns)/LPRI.
Sense resistor inductance (LRSENSE) is another source of
current limit error. LRSENSE creates an input offset voltage
(VOS) to the current comparator and causes the current
comparator to trip early. VOS can be calculated as:
V
OS = VTRANS
L
RSENSE
L
PRIMARY
The change in current limit becomes VOS/RSENSE.Theerror
is more signicant for applications using large di/dt ratios
in the transformer primary. It is recommended to use very
low inductance (< 2nH) sense resistors. Several resistors
can be placed in parallel to help reduce the inductance.
Care should also be taken in placement of the sense lines. The
negative return line, CSN, must be a dedicated trace to the low
sideresistorterminal.HaphazardlyroutingtheCSNconnection
to the ground plane can cause inaccurate current limit.
DONE and FAULT Pin Design
Both the DONE and FAULT pins require proper pull-up
resistors or current sources. Limit pin current to 1mA
into either of these pins. 100kΩ pull-up resistors are
recommended for most applications. Both the DONE and
FAULT pins are latched in the low output state. Resetting
either latch requires the CHARGE pin to be toggled. A
fault condition will also cause the DONE pin to go low.
A third, non-latching condition occurs during startup
when the CHARGE pin is driven high. During this start-up
condition, both the DONE and FAULT pins will go low for
several micro seconds. This indicates the internal rails
are still ramping to their proper levels. External RC lters
may be added to both indication pins to remove start-up
indication. Time constants for the RC lter should be
between 5μs to 20μs.
Under/Overvoltage Lockout
The LT3751 provides user-programmable under and
overvoltage lockouts for both VCC and VTRANS. Use the
equations in the Pin Functions section for proper selection
of resistor values. When under/overvoltage lockout
comparators are tripped, the master latch is disabled, power
delivery is halted, and the FAULT pin goes low. Adequate
supply bulk capacitors should be used to reduce power
supply voltage ripple that could cause false tripping during
normal switching operation.
The LT3751 provides internal Zener clamping diodes to
protect itself in shutdown when VTRANS is operated above
55V. Supply voltages should only be applied to UVLO1,
UVLO2, OVLO1 and OVLO2 with series resistance such
that the Absolute Maximum pin currents are not exceeded.
Pin current can be calculated using:
I
PIN =
V
APPLIED 55V
R
SERIES
Note that in shutdown, RVTRANS, RVOUT, RDCM, UVLO1,
UVLO2, OVLO1 and OVLO2 currents increase signicantly
when operating VTRANS above the Zener clamp voltages
and are inversely proportional to the external series pin
resistances.
NMOS Snubber Design
The transformer leakage inductance causes a parasitic
voltage spike on the drain of the power NMOS switch during
the turn-off transition. Transformer leakage inductance
effects become more apparent at high peak primary
currents. The worst-case magnitude of the voltage spike is
determined by the energy stored in the leakage inductance
and the total capacitance on the VDRAIN node.
V
D,LEAK =
L
LEAK I
2
PK
C
VDRAIN
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