參數(shù)資料
型號(hào)： LPC1226FBD64/301,1
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 14/61頁(yè)
文件大小： 0K
描述： MCU 32BIT 96K FLASH 8K 64-LQFP
產(chǎn)品培訓(xùn)模塊： LPC1200 Series for Industrial Control
特色產(chǎn)品： LPC122x Cortex-M0 Microcontrollers
標(biāo)準(zhǔn)包裝： 160
系列： LPC1200
核心處理器： ARM? Cortex?-M0
芯體尺寸： 32-位
速度： 45MHz
連通性： I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，POR，WDT
輸入/輸出數(shù)： 55
程序存儲(chǔ)器容量： 96KB（96K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-LQFP
包裝： 托盤(pán)
其它名稱(chēng)： 568-5162
LPC1226FBD64/301
LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
21 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I2C-bus can be used for test and diagnostic purposes.
The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.13 10-bit ADC
The LPC122x contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.13.1 Features
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to VDD(3V3).
10-bit conversion time of 257 kHz.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or counter/timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
7.14 Comparator block
The comparator block consists of two analog comparators.
7.14.1 Features
Up to six selectable external sources per comparator; fully configurable on either
positive or negative comparator input channels.
BOD 0.9 V internal reference voltage selectable on both comparators; configurable on
either positive or negative comparator input channels.
32-stage voltage ladder internal reference voltage selectable on both comparators;
configurable on either positive or negative comparator input channels.
Voltage ladder source voltage is selectable from an external pin or an internal 3.3 V
voltage rail if external power source is not available.
Voltage ladder can be separately powered down for applications only requiring the
comparator function.
Relaxation oscillator circuitry output for a feedback 555-style timer application.
Common interrupt connected to NVIC.
Comparator outputs selectable as synchronous or asynchronous.
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