參數(shù)資料
型號: LPC11U14FBD48/201,
廠商: NXP Semiconductors
文件頁數(shù): 21/72頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 32K 48LQFP
產(chǎn)品培訓(xùn)模塊: Code Density for LPC11xx
標(biāo)準(zhǔn)包裝: 250
系列: LPC11Uxx
核心處理器: ARM? Cortex?-M0
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,Microwire,智能卡,SPI,SSP,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 40
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 6K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-LQFP
包裝: 托盤
其它名稱: 568-8579
LPC11U1X
All information provided in this document is subject to legal disclaimers.
NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
28 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the USART.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC11U1x user manual.
7.16.6.4
APB interface
The APB peripherals are located on one APB bus.
7.16.6.5
AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
7.16.6.6
External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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