參數(shù)資料
型號(hào): LPC11E14FHN33/401,
廠商: NXP Semiconductors
文件頁數(shù): 6/8頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 32K 32HVQFN
產(chǎn)品培訓(xùn)模塊: Code Density for LPC11xx
標(biāo)準(zhǔn)包裝: 260
系列: LPC11Exx
核心處理器: ARM? Cortex?-M0
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 28
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 10K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 托盤
其它名稱: 568-8583
ES_LPC11E1X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Errata sheet
Rev. 2 — 1 February 2013
6 of 8
NXP Semiconductors
ES_LPC11E1x
Errata sheet LPC11E1x
4.
AC/DC deviations detail
4.1 n/a
5.
Errata notes detail
5.1 Note.1
The General Purpose I/O (GPIO) pins have configurable pull-up/pull-down resistors where
the pins are pulled up to the VDD level by default. During power-up, an unexpected glitch
(low pulse) could occur on the port pins as the VDD supply ramps up.
5.2 Note.2
For LPC11E14/401 devices with date codes 1238 and before, the 2 kB SRAM located at
address 0x20000000-0x20000800 is not available.
The 2 kB SRAM (0x20000000-0x20000800) is available for LPC11E14/401 devices with
date codes 1239 and later.
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