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參數(shù)資料
| 型號(hào)： | LP2975AIMM-12/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | MINI, SOP-8 |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大?。?/td> | 1135K |
| 代理商： | LP2975AIMM-12/NOPB |
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Application Hints (Continued)
tributions of phase lag and lead from each one. As shown in
the graphs, most of the phase lag (or lead) contributed by a
pole (or zero) occurs within one decade of the frequency of
the pole (or zero).
In general, a phase margin (defined as the difference be-
tween the total phase shift and 180) of at least 20 to 30
is required for a stable loop.
Effects of a Single Zero
10003426
Stability Analysis of Typical Applications
The first application to be analyzed is a fixed-output voltage
regulator with no feed-forward capacitor (see graph STABLE
PLOT WITHOUT FEED-FORWARD).
Stable Plot without Feed-Forward
10003427
In this example, the value of C
OUT is selected so that the
pole formed by C
OUT and RL (previously defined as fp)isset
at 200 Hz. The ESR of C
OUT is selected so that zero formed
by the ESR and C
OUT (defined as fz) is set at 5 kHz (these
selections follow the general guidelines stated previously in
this document). Note that the gate capacitance is assumed
to be moderate, with the pole formed by the C
GATE (defined
as f
pg) occurring at 100 kHz.
To estimate the total phase margin, the individual phase shift
contributions of each pole and zero will be calculated assum-
ing f
p = 200 Hz, fz = 5 kHz, fc = 10 kHz and fpg = 100 kHz:
Controller pole shift = 90
f
p shift = arctan (10k/200) = 89
f
z shift = arctan (10k/5k) = +63
f
pg shift = arctan (10k/100k) = 6
Summing the four numbers, the estimate for the total phase
shift is 122, which corresponds to a phase margin of 58.
This application is stable, but could be improved by using a
feed-forward capacitor (see next section).
EFFECT OF FEED-FORWARD: The example previously
used will be continued with the addition of a feed-forward
capacitor C
F
(see graph IMPROVED PHASE MARGIN
WITH FEED-FORWARD). The zero formed by C
F (previ-
ously defined as f
zf) is set at 10 kHz and the pole formed by
C
F (previously defined as fpf) is set at 40 kHz (the 4X ratio of
f
pf/fzf corresponds to VOUT = 5V).
Improved Phase Margin with Feed-Forward
10003428
To estimate the total phase margin, the individual phase shift
contributions of each pole and zero will be calculated assum-
ing f
p = 200 Hz, fz = 5 kHz, fzf = 10 kHz, fpf = 40 kHz,
f
c = 50 kHz, and fpg= 100 kHz:
Controller pole shift = 90
f
p shift = arctan (50k/200) = 90
f
z shift = arctan (50k/5k) = +84
f
zf shift = arctan (50k/100k) = +79
f
pf shift = arctan (50k/40k) = 51
f
pg shift = arctan (50k/100k) = 27
Summing the six numbers, the estimate for the total phase
shift is 95, which corresponds to a phase margin of 85
(a 27 improvement over the same application without the
feed-forward capacitor).
For this reason, a feed-forward capacitor is recommended in
all applications. Although not always required, the added
phase margin typically gives faster settling times and pro-
vides some design guard band against C
OUT and ESR varia-
tions with temperature.
Causes and Cures of Oscillations
The most common cause of oscillations in an LDO applica-
tion is the output capacitor ESR. If the ESR is too high or too
low, the zero (f
z) does not provide enough phase lead.
HIGH ESR: To illustrate the effect of an output capacitor with
high ESR, the previous example will be repeated except that
the ESR will be increased by a factor of 20X. This will cause
the frequency of the zero f
z to decrease by 20X, which
moves it from 5 kHz down to 250 Hz (see graph HIGH ESR
UNSTABLE WITHOUT FEED-FORWARD).
LP2975
www.national.com
17
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