參數(shù)資料
型號： LP2975AIMM-12/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO8
封裝： MINI, SOP-8
文件頁數(shù)： 11/20頁
文件大?。?/td> 1135K
代理商： LP2975AIMM-12/NOPB
Application Hints (Continued)
LOW OUTPUT VOLTAGE AND C
F
The feed-forward capacitor C
F will provide a positive phase
shift (lead) which can be used to cancel some of the excess
phase lag from any of the various poles present in the loop.
However, it is important to note that the effectiveness of C
F
decreases with output voltage.
This is due to the fact that the frequencies of the zero f
zf and
pole f
pf get closer together as the output voltage is reduced
(see equations in section FEED-FORWARD COMPENSA-
TION).
C
F is more effective when the pole-zero pair are farther
apart, because there is less self cancellation. The net benefit
in phase shift provided by C
F is the difference between the
lead (positive phase shift) from f
zf and the lag (negative
phase shift) from f
pf which is present at the crossover fre-
quency f
c. As the pole and zero frequency approach each
other, that difference diminishes to nothing.
The amount of phase lead at f
C provided by CF depends
both on the f
zf/fpf ratio and the location of fz with respect to fc.
To illustrate this more clearly, a graph is provided which
shows how much phase lead can be obtained for V
OUT =
12V, 5V, and 3.3V (see graph PHASE LEAD PROVIDED BY
C
F).
Phase Lead Provided by C
F
10003433
The most important information on the graph is the fre-
quency range of f
zf which will provide the maximum benefit
(most positive phase shift):
For V
OUT = 12V: 0.1 fc < fz < 1.0 fc
For V
OUT = 5V: 0.2 fc < fz < 1.2 fc
For V
OUT = 3.3V: 0.2 fc < fz < 1.3 fc
It’s also important to note how the maximum available phase
shift that C
F can provide drops off with VOUT. At 12V, more
than 50 can be obtained, but at 3.3V less than 30 is
possible. The lesson from this is that higher voltage designs
are more tolerant of phase shifts from both f
pg (the gate
capacitance pole) and incorrect placement of f
z
(which
means the output capacitor ESR is not at its nominal value).
At lower values of V
OUT, these parameters must be more
precisely selected since C
F can not provide as much correc-
tion.
GENERAL DESIGN PROCEDURE
Assuming that V
IN,VOUT, and RL are defined:
1) Calculate the required value of capacitance for C
OUT so
that the pole f
p
≤ 200 Hz (see previous section OUTPUT
CAPACITOR). For this calculation, an ESR of about 0.1
can be assumed for the purpose of determining C
OUT.
IMPORTANT: If a smaller value of output capacitor is used
(so that the value of f
p >200 Hz), the phase margin of the
control loop will be reduced. This will result in increased
ringing on the output voltage during a load transient. If the
output capacitor is made extremely small, oscillations will
result.
To illustrate this effect, scope photos have been presented
showing the output voltage of reference design #2 as the
output capacitor is reduced to approximately 1/30 of the
nominal value (the value which sets f
p = 200 Hz). As shown,
the effect of deviating from the nominal value is gradual and
the regulator is quite robust in resisting going into oscilla-
tions.
2) Approximate the crossover frequency f
c using the equa-
tion in the previous section CROSSOVER FREQUENCY
AND PHASE MARGIN.
3) Calculate the required ESR of the output capacitor so that
the frequency of the zero f
z is set to 0.5 fc (see previous
section OUTPUT CAPACITOR).
4) Calculate the value of the feed-forward capacitor C
F so
that the zero f
zf occurs at the frequency which yields the
maximum phase gain for the output voltage selected (see
previous section LOW OUTPUT VOLTAGE AND C
F). The
formula for calculating C
F is in the previous section FEED-
FORWARD CAPACITOR.
Lower ESR electrolytics are available which use organic
electrolyte (OSCON types), but are more costly than typical
aluminum electrolytics.
If the calculated value of ESR is higher than what is found in
the selected capacitor, an external resistor can be placed in
series with C
OUT.
LOW VOLTAGE DESIGNS: Designs which have a low out-
put voltage (where the positive effects of C
F are very small)
may be marginally stable if the C
OUT and ESR values are not
carefully selected.
Also, if the FET gate capacitance is large (as in the case of
a high-current FET), the pole f
pg could possibly get low
enough in frequency to cause a problem.
The solution in both cases is to increase the amount of
output capacitance which will shift f
p to a lower frequency
(and reduce overall loop bandwidth). The ESR and C
F cal-
culations should be repeated, since this changes the cross-
over frequency f
c.
LP2975
www.national.com
19
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