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參數(shù)資料
| 型號(hào)： | LMX2326SLBX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2800 MHz, CQCC16 |
| 封裝： | CSP-16 |
| 文件頁(yè)數(shù)： | 2/19頁(yè) |
| 文件大小： | 301K |
| 代理商： | LMX2326SLBX/NOPB |
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1.0 Functional Description (Continued)
1.3.1 POWERDOWN OPERATION
Bits F[2] and F[18] provide programmable powerdown modes when the CE pin is HIGH. When CE is LOW, the part is always
immediately disabled regardless of powerdown bit status. Refer to
Table 3.
Synchronous and asynchronous powerdown modes are both available by MICROWIRE selection. Synchronous powerdown
occurs if the F[18] bit (Powerdown Mode) is HIGH when F[2] bit (Powerdown) becomes HIGH. Asynchronous powerdown occurs
if the F[18] bit is LOW when its F[2] bit becomes HIGH.
In the synchronous powerdown mode (F[18] = HIGH), the powerdown function is gated by the charge pump to prevent unwanted
frequency jumps. Once the powerdown program bit F[2] is loaded, the part will go into powerdown mode after the first successive
charge pump event.
In the asynchronous powerdown mode (F[18] = LOW), the device powers down immediately after latching LOW data into bit F[2].
The device returns to an actively powered up condition in either synchronous or asynchronous mode immediately upon LE
latching LOW data into bit F[2].
Activation of a powerdown condition in either synchronous or asynchronous mode including CE pin activated powerdown has the
following effects:
Removes all active DC current paths.
Forces the R, N, and timeout counters to their load state
conditions.
Will TRI-STATE the charge pump.
Resets the digital lock detect circuitry.
Debiases the f
IN input to a high impedance state.
Disables the oscillator input buffer circuitry.
The MICROWIRE control register remains active and
capable of loading the data.
TABLE 3. Power Down Truth Table
CE(Pin 10)
F[2]
F[18]
Mode
LOW
X
Asynchronous Power Down
HIGH
0
X
Normal Operation
HIGH
1
0
Asynchronous Power Down
HIGH
1
Synchronous Power Down
TABLE 4. The Fo/LD (pin 14) Output Truth Table
F[3]
F[4]
F[5]
Fo/LD Output State
0
TRI-STATE
0
1
R Divider Output (fr)
0
1
0
N Divider Output (fp)
0
1
Serial Data Output
1
0
Digital Lock Detect (See 1.3.2 LOCK DETECT OUTPUT Section)
1
0
1
n Channel Open Drain Lock Detect (See 1.3.2 LOCK DETECT OUTPUT
Section)
1
0
Active HIGH
1
Active LOW
LMX2306/LMX2316/LMX2326
www.national.com
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