參數(shù)資料
型號(hào): LMC1982CIV
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類(lèi): 音頻控制
英文描述: Digitally-Controlled Stereo Tone and Volume Circuit with Two Selectable Stereo Inputs
中文描述: 2 CHANNEL(S), TONE CONTROL CIRCUIT, PQCC28
封裝: PLASTIC, LCC-28
文件頁(yè)數(shù): 3/14頁(yè)
文件大?。?/td> 348K
代理商: LMC1982CIV
Electrical Characteristics
(Continued)
The following specifications apply for V
+
= 9V, f
= 1 kHz, input signal (300 mV) applied to INPUT 1, volume = 0 dB, bass =
0 dB, treble = 0 dB, enhanced stereo is off, and loudness is off unlessotherwise specified. All limits apply for T
A
= T
J
= +25C.
Symbol
Parameter
Conditions
Typical
(Note 6)
Limit
(Note 7)
Unit
(Limit)
Channel-to-Channel Volume
Tracking Error
All Volume Attenuation Settings
from 0100010XXX101XXX (80 dB)
to 0100010XXX000000 (0 dB)
V
IN
= 1.0 V
rms
f
IN
= 100 Hz, Pins 13, 16
±
0.1
±
1.5
dB (min)
Mute Attenuation
Bass Gain Range
105
±
12
86
dB (max)
dB (min)
dB (max)
dB (max)
dB (min)
dB (max)
dB (min)
dB (max)
dB (max)
dB (min)
dB (max)
dB (min)
±
10.0
±
14.0
±
1.5
1.5
2.5
±
10.0
±
14.0
±
1.5
1.5
2.5
2.5
Bass Tracking Error
Bass Step Size
f
IN
= 100 Hz, Pins 13, 16
f
IN
= 100 Hz, Pins 13, 16
(Relative to Previous Level)
f
IN
= 10 kHz, Pins 13, 16
±
0.1
2.0
Treble Gain Range
±
12
Treble Tracking Error
Treble Step Size
f
IN
= 10 kHz, Pins 13, 16
f
IN
= 10 kHz, Pins 13, 16
(Relative to Previous Level)
(Note 10)
±
0.1
2.0
Enhanced Stereo Cross
Coupling
4.4
6.9
dB (max)
Frequency Response
V
IN
Applied to Input 1 and Input 2;
f
IN
= 20 Hz 20 kHz
(Relative to Signal Amplitude at 1 kHz)
Volume Attenuator = 40 dB, Loudness
on (See Figure 5)
Gain at 100 Hz (Referenced
to Gain at 1 kHz)
Gain at 10 kHz (Referenced
to Gain at 1 kHz)
V
IN
= 1.0 V
rms
, A Weighted,
Measured at 1 kHz, R
S
= 470
All Volume Settings
Input Pins 4, 25: Output Pins 13, 16;
V
IN
= 1.0V
rms
(Note 8)
470
to AC Ground on Unused Input
V
+
= 9 V
DC
; 200 mV
rms
, 100 Hz
Sinewave Applied to Pin 26
±
0.1
±
1.0
dB (max)
Loudness
11.5
13.5
9.5
8.5
4.5
90
dB (max)
dB (min)
dB (max)
dB (min)
dB (min)
6.5
Signal-to-Noise Ratio
95
Channel Balance
Channel Separation
0.2
80
1.0
60
dB (max)
dB (min)
Input-Input Isolation
Power Supply Rejection Ratio
95
32
60
28
dB (min)
dB (min)
PSSR
f
CLK
Clock Frequency
5.0
1.0
MHz
(max)
V (min)
V (min)
V (max)
V (max)
V (min)
V (max)
V
IN(1)
Logic “1” Input Voltage
Pins 1, 27, 28 (IM Bus)
Pins 2, 3
Pins 1, 27, 28 (IM Bus)
Pins 2, 3
Pin 28 (IM Bus)
Pin 28 (IM Bus)
1.3
2.9
0.4
1.2
2.0
5.5
0.8
3.5
2.0
0.8
V
IN(0)
Logic “0” Input Voltage
V
OUT(1)
V
OUT(0)
Logic “1” Output Voltage
Logic “0” Output Voltage
0.4
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the deivce may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2:
All voltages are specified with respect to ground.
Note 3:
When the input voltage (V
IN
) at any pin exceeds the power supply voltages (V
IN
<
V
or V
IN
>
V
+
) the absolute value of the current at that pin should be
limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply voltages with 5 mA current limit to four.
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