參數(shù)資料
型號(hào): LM98714
廠(chǎng)商: National Semiconductor Corporation
英文描述: Three Channel, 16-Bit, 45 MSPS Digital Copier Analog Front End with Integrated CCD/CIS Sensor Timing Generator and LVDS Output
中文描述: 三通道,16位,45 MSPS的數(shù)碼復(fù)印機(jī)模擬前端與綜合防治荒漠化公約/獨(dú)聯(lián)體傳感器時(shí)序發(fā)生器和LVDS輸出
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 604K
代理商: LM98714
Electrical Characteristics
(Continued)
The following specifications apply for VA = VD = VR = VC = 3.3V, C
= 10pF, and f
INCLK
= 15MHz unless otherwise specified.
Boldface limits apply for T
A
= T
MIN
to T
MAX
;
all other limits T
A
= 25C.
Symbol
V
IHC
Parameter
CMOS Clock
High Threshold Voltage
CMOS Clock
Low Threshold Voltage
CMOS Clock
Input High Current
CMOS Clock
Input Low Current
Conditions
INCLK- = DGND
Min
2.0
Typ
(Note 8)
Max
Units
V
V
ILC
0.8
V
I
IHL
280
μA
I
ILC
-150
μA
LVDS Output DC Specifications
V
OD
Differential Output Voltage
V
OS
LVDS Output Offset Voltage
I
OS
Output Short Circuit Current
Power Supply Specifications
IA
VA Analog Supply Current
R
L
= 100
180
1.17
328
1.23
7.9
450
1.3
mV
V
mA
V
OUT
= 0V, R
L
= 100
VA Normal State
VA Low Power State
(Powerdown)
VR Normal State
(LVDS Outputs)
CMOS Output Data Format
LVDS Output Data Format
with Data Outputs Disabled
LVDS Output Data Format
CMOS Output Data Format
(ATE Loading of CMOS
Outputs
>
50pF)
Typical sensor outputs:
SH, CLK1=
Φ
1A, CLK2=
Φ
2A,
CLK3=
Φ
B, CLK4=
Φ
C,
CLK5=RS, CLK6=CP
(ATE Loading of CMOS
Outputs
>
50pF)
LVDS Output Data Format
CMOS Output Data Format
(ATE Loading of CMOS
Outputs
>
50pF)
60
12
97
23
125
32
mA
mA
IR
VR Digital Supply Current
30
64
75
mA
15
47
47
55
mA
mA
ID
VD Digital Output Driver Supply
Current
0.05
mA
mA
12
40
IC
VC CCD Timing Generator
Output Driver Supply Current
0.5
12
mA
PWR
Average Power Dissipation
350
380
505
610
650
700
mW
mW
Input Sampling Circuit Specifications
V
IN
Input Voltage Level
CDS Gain=1x, PGA Gain=1x
CDS Gain=2x, PGA Gain=
1x
2.3
1.22
Vp-p
L
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