參數(shù)資料
型號: LM98714
廠商: National Semiconductor Corporation
英文描述: Three Channel, 16-Bit, 45 MSPS Digital Copier Analog Front End with Integrated CCD/CIS Sensor Timing Generator and LVDS Output
中文描述: 三通道,16位,45 MSPS的數(shù)碼復(fù)印機模擬前端與綜合防治荒漠化公約/獨聯(lián)體傳感器時序發(fā)生器和LVDS輸出
文件頁數(shù): 5/12頁
文件大?。?/td> 604K
代理商: LM98714
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
Name
I/O
O
O
O
O
I
I
I/O
I
I
Typ
D
D
D
D
D
D
D
D
D
P
P
Res
PU
PD
PU
PD
PU
PD
Description
CLK3
CLK2
CLK1
SH
RESET
SH_R
SDIO
SCLK
SEN
AGND
V
A
Configurable sensor control output.
Configurable sensor control output.
Configurable sensor control output.
Sensor - Shift or transfer control signal for CCD and CIS sensors.
Active-low master reset. NC when function not being used.
External request for an SH pulse.
Serial Interface Data Input
Serial Interface shift register clock.
Active-low chip enable for the Serial Interface.
Analog ground return.
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to
AGND.
Bottom of ADC reference. Bypass with a 0.1μF capacitor to ground.
Top of ADC reference. Bypass with a 0.1μF capacitor to ground.
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to
AGND.
Analog ground return.
Input Clamp Voltage. Normally bypassed with a 0.1μF, and a 4.7μF capacitor to
AGND. An external reference voltage may be applied to this pin.
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to
AGND.
Analog ground return.
Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.
Analog ground return.
Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.
Analog ground return.
Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.
Analog ground return.
Digital ground return.
Power supply input for internal voltage reference generator. Bypass this supply
pin with a 0.1μF capacitor.
Digital Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to
DGND.
Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS
clock is selected when pin 29 is held at DGND, otherwise clock is configured
for LVDS operation.
Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.
Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in
LVDS Mode.
PD
PU
12
13
14
VREFB
VREFT
V
A
O
O
A
A
P
15
16
AGND
VCLP
P
A
IO
17
V
A
P
18
19
20
21
22
23
24
25
26
AGND
OS
R
AGND
OS
G
AGND
OS
B
AGND
DGND
V
R
P
A
P
A
P
A
P
P
P
I
I
I
27
DVB
O
P
28
INCLK+
I
D
29
30
INCLK-
DOUT7/
TXCLK+
DOUT6/
TXCLK-
DOUT5/
TXOUT2+
DOUT4/
TXOUT2-
DOUT3/
TXOUT1+
DOUT2/
TXOUT1-
I
O
D
D
31
O
D
Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in
LVDS Mode.
32
O
D
Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS
Mode.
33
O
D
Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS
Mode.
34
O
D
Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS
Mode.
35
O
D
Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS
Mode.
L
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