參數(shù)資料
型號： LM98555CCMH
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 時鐘及定時
英文描述： CCD Driver
中文描述： 98555 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO64
封裝： EXPOSED PAD, TSSOP-64
文件頁數(shù)： 3/9頁
文件大?。?/td> 691K
代理商： LM98555CCMH
Pin Descriptions
Symbol
Driver inputs
P2B
IN
RS
IN
CP
IN
P1A
IN
P2A
IN
SH
IN
AFE
IN
MCL
IN
SHD
IN
Driver Outputs
SHD
OUT
Pin
Type
Description
8
9
10
15
18
21
22
23
24
Input
Input
Input
Input
Input
Input
Input
Input
Input
CMOS logic input for the P2B driver.
CMOS logic input for the RS driver.
CMOS logic input for the CP driver.
CMOS logic input for the P1A ganged (8) driver set.
CMOS logic input for the P2A ganged (8) driver set.
CMOS logic input for the SH ganged (3) driver set.
CMOS logic input for the AFE driver.
CMOS logic input for the MCL driver.
CMOS logic input for the SHD driver.
28
Output;
Low-Strength
Output;
Low-Strength
Output;
Low-Strength
Output;
Low-Strength
Output;
Low-Strength
Output;
Low-Strength
Output;
TRI-STATE
;
High-Strength
Driver output for the SHD
IN
input signal.
MCL
OUT
30
Driver output for the MCL
IN
input signal.
AFE
OUT
31
Driver output for the AFE
IN
input signal.
CP
OUT
2
Driver output for the CP
IN
input signal. Typically used to drive the Clamp
Gate input of the CCD.
Driver output for the RS
IN
input signal. Typically used to drive the Reset
Gate input of the CCD.
Driver output for the P2B
IN
input signal.
RS
OUT
3
P2B
OUT
5
P2A
OUT0
P2A
OUT1
P2A
OUT2
P2A
OUT3
P2A
OUT4
P2A
OUT5
P2A
OUT6
P2A
OUT7
P1A
OUT0
P1A
OUT1
P1A
OUT2
P1A
OUT3
P1A
OUT4
P1A
OUT5
P1A
OUT6
P1A
OUT7
SH
OUT0
SH
OUT1
SH
OUT2
Logic Inputs
EN0
EN1
47
46
43
42
39
38
35
34
50
51
54
55
58
59
62
63
26
27
6
Ganged driver outputs for the P2A
IN
input. Typically the user may join
together these outputs to drive the
φ
2 clock input of the CCD. Some of
these outputs may be disabled using the EN(1:0) inputs - see the
Functional Description section.
Output;
TRI-STATE;
High-Strength
Ganged driver outputs for the P1A
IN
input. Typically the user may join
together these outputs to drive the
φ
1 clock input of the CCD. Some of
these outputs may be disabled using the EN(1:0) inputs - see the
Functional Description section.
Output;
Low-Strength
Ganged driver outputs for the SH
IN
input signal. Typically used to drive the
Shift Gate input of the CCD.
11
12
Input
Driver enable control. Some of the P1A and P2A drivers can be disabled
using these inputs. See the Functional Description section.
L
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