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參數資料
| 型號： | LM9823CCWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | LM9823 3 Channel 48-Bit Color Scanner Analog Front End |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-28 |
| 文件頁數： | 6/22頁 |
| 文件大?。?/td> | 244K |
| 代理商： | LM9823CCWM |
6
www.national.com
Note 7:
Two diodes clamp the OS analog inputs to AGND and V
A
as shown below. This input protection, in combination with the external clamp capacitor and the output
impedance of the sensor, prevents damage to the LM9823 from transients during power-up.
Note 8:
To guarantee accuracy, it is required that V
and V
be connected to clean, low noise power supplies, with separate bypass capacitors at each supply pin. When
both V
A
and V
D
are operated at 5.0V, they must be powered by the same regulator, with separate power planes or traces and separate bypass capacitors at each supply pin.
Note 9:
Typicals are at T
J
=T
A
=25°C, f
MCLK
= 12MHz, and represent most likely parametric norm.
Note 10:
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11:
Full channel integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer
function of the AFE.
Note 12:
The sensor’s maximum peak differential signal range is defined as the peak sensor output voltage for a white (full scale) image, with respect to the dark reference
level.
Note 13:
PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula
V
V
31
where
.
Note 14:
Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, DOE = 0, and a single OS input with a gain register setting of 1 (000001b) and
an offset register setting of 0 (000000b).
Note 15:
The digital supply current (I
D
) does not include the load, data and switching frequency dependent current required to drive the digital output bus on pins (D7 - D0).
The current required to switch the digital data bus can be calculated from: I
SW
= 2*N
D
*P
SW
*C
L
*V
D
/t
MCLK
where N
D
is total number of data pins, P
SW
is the probability of
each data bit switching, C
L
is the capacitive loading on each data pin, V
D
is the digital supply voltage and t
MCLK
is the period of the MCLK input. For most applications, N
D
is 8, P
SW
is
≈
0.5, and V
D
is 5V, and the switching current can be calculated from: I
SW
= 40*C
L
/t
MCLK
. (With V
D
at 3.3V, the equation becomes: I
SW
= 26.4*C
L
/t
MCLK
.) For
example, if the capacitive load on each digital output pin (D7 - D0) is 20pF and the period of t
MCLK
is 1/12MHz or 83ns, then the digital switching current would be 9.6mA.
The calculated digital switching current will be drawn through the V
D
pin and should be considered as part of the total power budget for the LM9823.
Note 16:
All specifications quoted in LSBs are based on 12 bit resolution.
OS Input
AGND
V
A
TO INTERNAL
CIRCUITRY
V
WHITE
V
REF
V
RFT
CCD Output Signal
CIS Output Signal
V
WHITE
Black Level
GainPGA
---
G0
X--------------------------
+
=
X
G31
G0
–
(
)
32
-----
=
AC Electrical Characteristics
(Continued)
L
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LM9823CCWMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM9823 3 Channel 48-Bit Color Scanner Analog Front End |
| LM9830 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM9830 36-Bit Color Document Scanner |
| LM9830VJD | 功能描述:視頻模擬/數字化轉換器集成電路 RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數量:1 ADC 輸入端數量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| LM9830VJD/NOPB | 功能描述:視頻模擬/數字化轉換器集成電路 RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數量:1 ADC 輸入端數量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| LM9830VJDX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM9830 36-Bit Color Document Scanner |
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