參數(shù)資料
型號(hào)： LM9820CCWMX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO20
封裝： PLASTIC, SOIC-20
文件頁(yè)數(shù)： 7/21頁(yè)
文件大小： 148K
代理商： LM9820CCWMX
7
http://www.national.com
Note 7:
Two diodes clamp the OS analog inputs to
AGND
and
VA
as shown below. This input protection, in combination with the external clamp capacitor and the output
impedance of the sensor, prevents damage to the LM9810/20 from transients during power-up.
Note 8:
To guarantee accuracy, it is required that VA and VD be connected together to the same power supply with separate bypass capacitors at each supply pin.
Note 9:
Typicals are at T
J
=T
A
=25°C, f
MCLK
= 24MHz, and represent most likely parametric norm.
Note 10:
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11:
Integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the
ADC.
Note 12:
V
is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. V
is defined as the peak CCD pixel output voltage for
a white (full scale) image with respect to the reference level, V
.
V
is defined as the peak positive deviation above V
of the reset feedthrough pulse. The maximum
correctable range of pixel-to-pixel V
variation is defined as the maximum variation in V
WHITE
(due to PRNU, light source intensity variation, optics, etc.) that the
LM9810/20 can correct for using its internal PGA.
Note 13:
PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula
where
.
GainPGA
V
31
Note 14:
Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, and a single OS input with a gain register setting of 1 (000001b) and an offset
register setting of 0 (000000b).
Note 15:
The digital supply current (I
D
) does not include the load, data and switching frequency dependent current required to drive the digital output bus on pins (
D5
-
D0
).
The current required to switch the digital data bus can be calculated from: Isw = 2*Nd*Psw*CL*
VD
/tSampCLK where Nd is total number of data pins, Psw is the probability
of each data bit switching, CL is the capacitive loading on each data pin,
VD
is the digital supply voltage and tSampCLK is the period of the
SampCLK
signal. Since Nd is
6, Psw should be .5, and
VD
is nominally 5V, the switching current can usually be calculated from: Isw = 30*CL/tSampCLK. For example, if the capacitive load on each dig-
ital output pin (
D5
-
D0
) is 20pF and the period of tSampCLK is 1/6MHz or 167ns , then the digital switching current would be 7.2mA. The calculated digital switching current
will be drawn through the
VD
pin and should be considered as part of the total power budget for he LM9810/20.
OS Input
AGND
VA
TO INTERNAL
CIRCUITRY
V
WHITE
V
REF
V
RFT
CCD Output Signal
V
---
G0
X--------------------------
+
=
X
G31
G0
–
(
)
32
------
=
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