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參數(shù)資料
| 型號： | LM9820CCWMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | LM9810/20 10/12-Bit Image Sensor Processor Analog Front End |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大小： | 148K |
| 代理商： | LM9820CCWMX |
18
http://www.national.com
approximately 2mV. If there are 2700 active pixels on a line then:
2.1.3 Maximum Clamp Capacitor Calculation:
The maximum size of the clamp capacitor is determined by the
amount of time available to charge it to the desired value during
the optical black portion of the sensor output. The internal clamp
is on when
NewLine
is high and
SampCLK
is low. If the applied
SampCLK
is low for half its cycle, then the available charge time
per line can be calculated using:
SampCLK
Equation 13: Clamp Time Per Line Calculation
For example, if a sensor has 18 black reference pixels and f
Samp-
CLK
is 2MHz with a 50% duty cycle, then t
CLAMP
is 4.5μs.
The following equation takes the number of optical black pixels,
the amount of time (per pixel) that the clamp is closed, the sen-
sor’s output impedance, and the desired accuracy of the final
clamp voltage and provides the maximum clamp capacitor value
that allows the clamp capacitor to settle to the desired accuracy
within a single line:
t
R
Equation 14: C
CLAMP MAX
for a single line of charge time
Where t
CLAMP
is the amount of time (per line) that the clamp is
on, R
CLAMP
is the output impedance of the CCD plus 50
for the
LM9810/20’s internal clamp switch, and accuracy is the ratio of
the worst-case initial capacitor voltage to the desired final capaci-
tor voltage. If t
CLAMP
is 4.5μs, the output impedance of the sen-
sor is 1500
, the worst case voltage change required across the
capacitor (before the first line) is 5V, and the desired accuracy
after clamping is to within 0.1V (accuracy = 5/0.1 = 50), then:
The final value for C
CLAMP
should be less than or equal to
C
CLAMP MAX
, but no less than C
CLAMP MIN
.
In some cases, depending primarily on the choice of sensor,
C
CLAMP MAX
may actually be lessthan C
CLAMP MIN
, meaning that
the capacitor can not be charged to its final voltage during the
black pixels at the beginning of a line and hold it’s voltage without
drooping for the duration of that line. This is usually not a problem
because in most applications the sensor is clocked continuously
as soon as power is applied. In this case, a larger capacitor can
be used (guaranteeing that the C
CLAMP MIN
requirement is met),
and the final clamp voltage is forced across the capacitor over
multiple lines. This equation calculates how many lines are
required before the capacitor settles to the desired accuracy:
Equation 16: Number of Lines Required for Clamping
Using the values shown before and a clamp capacitor value of
0.01μF, this works out to be:
1550-------------------
μ
F
μ
s
Equation 17: Clamping Lines Required Example
In this example, a 0.01μF capacitor takes 14 lines after power-up
to charge to its final value. On subsequent lines, the only error will
be the droop across a single line which should be significantly
less than the initial error.
If the LM9810/20 is operating in CDS
mode and multiple lines are used to charge up the clamping
capacitors after power-up, then a clamp capacitor value of
0.01μF should be significantly greater than the calculated
C
CLAMP MIN
value and can virtually always be used.
If the LM9810/20 is operating in CIS mode, then significantly
larger clamp capacitors must be used. Fortunately, the output
impedance of most CIS sensors is significantly smaller than the
output impedance of CCD sensors, and R
CLAMP
will be domi-
nated by the 50
from the LM9810/20’s internal clamp switch.
With a smaller R
CLAMP
value, the clamp capacitors will charge
faster.
3.0 Performance Considerations
3.1 Power Supply
The LM9810/20 should be powered by a single +5V source. The
analog supplies (
VA
) and the digital supply (
VD
) are brought out
individually to allow separate bypassing for each supply input.
They should not be powered by two or more different supplies.
In systems with separate analog and digital +5V supplies, all the
supply pins of the LM9810/20 should be powered by the analog
+5V supply. Each supply input should be bypassed to its respec-
tive ground with a 0.1μF capacitor located as close as possible to
the supply input pin. A single 10μF tantalum capacitor should be
placed near the
VA
supply pin to provide low frequency bypass-
ing.
To minimize noise, keep the LM9810/20 and all analog compo-
nents as far as possible from noise generators, such as switching
power supplies and high frequency digital busses. If possible, iso-
late all the analog components and signals (OS, reference inputs
and outputs,
VA
,
AGND
) on an analog ground plane, separate from
the digital ground plane. The two ground planes should be tied
together at a single point, preferably the point where the power
supply enters the PCB.
3.2 SampCLK Timing
SampCLK
is used to time the stages of the LM9810/20’s sampler,
offset DAC and programmable gain amplifier. To allow for opti-
mum input signal sampling times,
SampCLK
may be applied asyn-
chronously to
MCLK
. The LM9810/20’s ADC is synchronized with
the its AFE (including the sampler, the offset DAC and the PGA)
by
MCLK
.
The LM9810/20’s internal ADC clock is created through a combi-
CCLAMP MIN
5.4uF
42mV
=
Equation 12: CIS mode C
CLAMP MIN
Calculation Example
=
t
CLAMP
Number 2f
=
CCLAMP MAX
-----
ln(ac 1
=
RCLAMP
ln(accuracy)
=
CCLAMP MAX
μ
s
728pF
1550
ln(50)
=
=
Equation 15: C
CLAMP MAX
Example
lines
RCLAMP
tCLAMP
Final Error Voltage
ln
=
lines
0.1V
ln
13.5 lines
=
=
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