參數(shù)資料
型號(hào)： LM9810CCWM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO20
封裝： PLASTIC, SOIC-20
文件頁(yè)數(shù)： 17/21頁(yè)
文件大?。?/td> 148K
代理商： LM9810CCWM
17
http://www.national.com
Equation 6: Simplified output code calculation
1.8 Power Down Mode
Setting the Power Down (bit B0 of register 7) puts the device in a
low power standby mode. The analog sections are turned off to
conserve power. The digital logic will continue to operate if
MCLK
continues, so for minimum power dissipation
MCLK
should be
stopped when the LM9810/20 enters the Power Down mode.
Recovery from Power Down typically takes 50μs (the time
required for the reference voltages to settle to 0.5 LSB accuracy).
2.0 Clamping
To perform a DC restore across the AC coupling capacitors at the
beginning of every line, the LM9810/20 implements a clamping
function. When
NewLine
is high and
SampCLK
is low, all three OS
inputs will be connected to either
V
or
V
, depending on B4
of the Sampling and Color Mode register. If B4 is set to one (pos-
itive signal polarity), then the OS inputs will be connected to
V
. If B4 is set to zero (negative signal polarity), then they will be
connected to
V
REF+
.
2.1 Clamp Capacitor Selection
This section explains how to select appropriate clamp capacitor
values.
The output signal of many sensors rides on a DC offset (greater
than 5V for many CCDs) which is incompatible with the
LM9810/20’s 5V operation. To eliminate this offset without resort-
ing to additional higher voltage components, the output of the
sensor is AC coupled to the LM9810/20 through a DC blocking
capacitor, C
CLAMP
. The sensor’s DOS output, if available, is not
used. The value of this capacitor is determined by the leakage
current of the LM9810/20’s OS input and the output impedance of
the sensor. The leakage through the OS input determines how
quickly the capacitor value will drift from the clamp value of
V
REF+
or
V
REF-
, which then determines how many pixels can be pro-
cessed before the droop causes errors in the conversion (±0.1V
is the recommended limit for CDS operation). The output imped-
ance of the sensor determines how quickly the capacitor can be
charged to the clamp value during the black reference period at
the beginning of every line.
The minimum clamp capacitor value is determined by the maxi-
mum droop the LM9810/20 can tolerate while converting one
sensor line. The minimum clamp capacitor value is much smaller
for CDS mode applications than it is for CIS mode applications.
The LM9810/20 input leakage current is considerably less when
the LM9810/20 is operating in CDS mode. In CDS mode, the
LM9810/20 leakage current should be no more than 20nA. With
CDS disabled, which will likely be the case when CIS sensors are
used, the LM9810/20 leakage current can be as high as 25uA at
the maximum conversion rate.
2.1.1 CDS mode Minimum Clamp Capacitor Calculation:
The following equation takes the maximum leakage current into
the OS input, the maximum allowable droop, the number of pixels
on the sensor, and the pixel conversion rate, f
SampCLK
, and pro-
vides the minimum clamp capacitor value:
For example, if the OS input leakage current is 20nA worst-case,
the sensor has 2700 active pixels, the conversion rate is 2MHz
(t
SampCLK
= 500ns), and the max droop desired is 0.1V, the mini-
mum clamp capacitor value is:
2.1.2 CIS mode Minimum Clamp Capacitor Calculation:
If CDS is disabled, then the maximum LM9810/20 OS input leak-
age current can be calculated from:
where V
SAT
is the peak pixel signal swing of the CIS OS output
and C
SAMP
is the capacitance of the LM9810/20’s internal sam-
pling capacitor (2pF). Inserting this into Equation 7 results in:
with C
SAMP
equal to 2pF and V
SAT
equal to 2V (the LM9810/20’s
maximum input signal), then Equation 10 reduces to:
In CIS mode (CDS disabled), the max droop limit must be much
more carefully chosen, since any change in the clamp capacitor’s
DC value will affect the LM9810/20’s conversion results. If a
droop of one 10 bit LSB across a line is considered acceptable,
then the allowed droop voltage is calculated as: 2V/1024, or
D
OUT
V
IN
G
B
V
DAC
+
(
)
G
PGA
C
=
DOS
OS
OS
SENSOR
NC
C
CLAMP
Figure 5: OS Clamp Capacitor and Internal Clamp
V
REF+
or
V
REF-
LM9810/20
CCLAMP MIN
dV
-- i
=
leakage current (A)
-------max droop(V)
SampCLK
--------f
=
Equation 7: CDS mode C
CLAMP MIN
Calculation
CCLAMP MIN
20nA
270pF
-0.1V
2MHz
=
=
Equation 8: CDS mode C
CLAMP MIN
Example
I
leakage
V
SAT
f
SampCLK
C
SAMP
=
Equation 9: CIS mode Input Leakage Current Calculation
CCLAMP MIN
dV
--- i
=
V
SampCLK
t
SAMP
t
max droop(V)
=
Equation 10: CIS mode C
CLAMP MIN
Calculation
CCLAMP MIN
max droop(V)
=
Equation 11: CIS mode C
CLAMP MIN
Calculation
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