參數(shù)資料
型號(hào)： LM9810CCWM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO20
封裝： PLASTIC, SOIC-20
文件頁(yè)數(shù)： 15/21頁(yè)
文件大?。?/td> 148K
代理商： LM9810CCWM
15
http://www.national.com
Applications Information
1.0 Programming the LM9810/20
1.1 Writing to the Configuration Register
When
NewLine
is high,
D2
,
D1
&
D0
act as a serial interface for writ-
ing to the configuration registers.
D2
is the input serial clock
(SCLK),
D0
is the input data pin (SDI), and
D1
is the latch and
shift enable signal (Latch). When
D1
(Latch) is low, serial data is
shifted into
D0
(SDI), and must be valid on each rising edge of
D2
(SCLK). Three register address bits followed by six data bits
should be shifted into
D0(SDI),
MSB first. When
D1
(Latch) transi-
tions from low to high, the last 6 data bits will be stored into the
configuration register addressed by the previous 3 address bits
(as shown in Diagram 3).
D1
(Latch) must remain high for at least
3 cycles of the serial clock on
D2
(SCLK) to write to the configura-
tion register.
1.2 CDS Mode
The LM9810/20 uses a high-performance CDS (Correlated Dou-
ble Sampling) circuit to remove many sources of noise and error
from the CCD signal. It also supports CIS image sensors with a
single sampling mode.
Figure 1 shows the output stage of a typical CCD and the result-
ing output waveform:
Figure 1: CDS
Capacitor C1 converts the electrons coming from the CCD’s shift
register to an analog voltage. The source follower output stage
(Q2) buffers this voltage before it leaves the CCD. Q1 resets the
voltage across capacitor C1 between pixels at intervals 2 and 5.
When Q1 is on, the output signal (OS) is at its most positive volt-
age. After Q1 turns off (period 3), the OS level represents the
residual voltage across C1 (V
RESIDUAL
). V
RESIDUAL
includes
charge injection from Q1, thermal noise from the ON resistance
of Q1, and other sources of error. When the shift register clock
(1) makes a low to high transition (period 4), the electrons from
the next pixel flow into C1. The charge across C1 now contains
the voltage proportional to the number of electrons plus V
RESID-
UAL
, an error term. If OS is sampled at the end of period 3 and
that voltage is subtracted from the OS at the end of period 4, the
V
RESIDUAL
term is canceled and the noise on the signal is
reduced ([V
SIGNAL
+V
RESIDUAL
]-V
RESIDUAL
= V
SIGNAL
). This is the
principal of Correlated Double Sampling.
If the LM9810/20 is programmed for correlated double sampling
(bit B5 of register 0 is cleared), then the falling edge of
SampCLK
should occur toward the end of period 3 and the rising edge of
SampCLK
should occur towards the end of period 4. While
Samp-
CLK
is high, the Reference level (V
RESIDUAL
) is sampled, and it is
held at the falling edge of
SampCLK
. While
SampCLK
is low, the sig-
nal level (V
SIGNAL
+ V
RESIDUAL
) is sampled and it is held at the ris-
ing edge of
SampCLK
. The output from the sampler is the potential
difference between the two samples, or V
SIGNAL
.
1.3 CIS Mode
The LM9810/20 supports CIS (Contact Image Sensor) devices by
offering a sampling mode for capturing positive going signals, as
opposed to the CCD’s negative going signal. The output signal of
a CIS sensor (Figure 2) differs from a CCD signal in two primary
ways: its output increases with increasing signal strength, and it
does not usually have a reference level as an integral part of the
output waveform of every pixel.
Figure 2: CIS
When the LM9810/20 is in CIS mode (Register 0, B5=1), it uses
either
V
REF+
or
V
REF-
depending on the signal polarity setting (B4
of the Sampling and Color Mode register) as the reference (or
black) voltage for each pixel. If the signal polarity is set to one,
then
V
REF-
will be held on the falling edge of
SampCLK
and the OS
signal will be held on the rising edge of
SampCLK
. If it is set to
zero, then
V
REF+
will be held on the falling edge of
SampCLK
and
the OS signal will be held on the rising edge of
SampCLK
. The ris-
ing edge of
SampCLK
should occur near the end of period 4, and
at least 50ns after the falling edge of
SampCLK
.
1.4 Multiplexer/Channel Switching
The offset and gain settings automatically switch after each ADC
conversion according to the color mode setting in the Sampler
and Color Mode register (register 0). For example, if the color
mode (bits B2,B1 & B0) is set to 001, the offset and gain will alter-
nately switch between the R, G and B settings after each conver-
sion. The input multiplexer never changes during a line, but if the
color mode is set to Line Rate Color (000), the mux will automati-
cally switch after each new line.
The offset and gain settings will always start with the first channel
of the programmed mode after a falling edge on
NewLine
. For
RS (RESET)
e-
(from shift register)
OS
Q1
Q2
C1
V
DD
V
SS
1
RS
OS
1
2
3
4
5
SampCLK
OS (CCD)
1
2
3
4
5
OS (CIS)
SampCLK
相關(guān)PDF資料
PDF描述
LM9820CCWM LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
LM9810CCWMX LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
LM9820CCWMX LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
LM9812 LM9812 30-Bit Color Linear CCD Sensor Processor
LM9812CCV LM9812 30-Bit Color Linear CCD Sensor Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LM9810CCWMX 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
LM9811 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor
LM9811CCV 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor
LM9811CCVF 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor
LM9812 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM9812 30-Bit Color Linear CCD Sensor Processor
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*