參數(shù)資料
型號： LM9627CCEA
廠商： National Semiconductor Corporation
英文描述： BZ Series Standard Basic Switch, Single Pole Double Throw Circuitry, 15 A at 125 Vac, Overtravel Plunger Actuator, 2,5 N - 3,61 N [9 oz - 13 oz] Operating Force, Silver Contacts, Screw Termination, CE, CSA, DEMKO,
中文描述： 彩色CMOS圖像傳感器顯卡30醫(yī)科
文件頁數(shù)： 21/37頁
文件大?。?/td> 370K
代理商： LM9627CCEA
Confidential
21
www.national.com
Functional Description
(continued)
,
Figure 36.
pclk
in Data Ready Mode
By default the pixel clock is a free running active low (pixel data
changes on the positive edge of the clock) with a period equal to
the internal
hclk
. The active edge of the clock can be pro-
grammed such that pixel data changes on the positive or nega-
tive edge of the clock.
14.3
The horizontal synchronisation output pin,
hsync
, is used as an
indicator for row data. The hsync output pin can be programmed
to operate in two modes as follows:
Horizontal Synchronisation Output Pin (hsync)
Level mode should be used when the pixel clock,
pclk,
is pro-
grammed to operate in
free running mode.
In level mode the
hsync
output pin will go to the specified level (high or low) at
the start of each row and remain at that level until the last
pixel of that row is read out on d[11:0] as shown in Figure 37.
The
hsync
level is always synchronized to the active edge of
pclk
.
Figure 37.
hsync
in Level Mode
Pulse mode should be used when the pixel clock,
pclk,
is pro-
grammed to operate in
data ready mode.
In pulse mode the
hsync
output pin will produce a pulse at the end of each row.
The width of the pulse will be a minimum of four
pclk
cycles
and its polarity can be programmed as shown in Figure 38.
The
hsync
level is always synchronized to the active edge of
pclk
Figure 38.
hsync
in Pulse Mode
By default the first pixel data at the beginning of each row is
placed on the digital video bus as soon as
hsync
is activated. It
is possible to program up to 15 dummy pixels to be readout at
the beginning of each row before the real pixel data is readout.
This feature is supported for both
level
and
pulse
mode.
14.4
The vertical synchronisation output pin,
vsync,
is used as an
indicator for pixel data within a frame. The
vsync
output pin can
be programmed to operate in two modes as follows:
Vertical/Horizontal Synchronisation Pin (vsync)
Level mode should be used when the pixel clock,
pclk,
is pro-
grammed to operate in
free running mode.
In level mode the
vsync
output pin will go to the specified level (high or low) at
the start of each frame and remain at that level until the last
pixel of that row in the frame is placed on d[11:0] as shown in
Figure 39. The
hsync
level is always synchronized to the
active edge of
pclk
.
Figure 39. vsync in Level Mode
Pulse mode should be used when the pixel clock,
pclk,
is pro-
grammed to operate in
data ready mode.
In pulse mode the
vsync
output pin will produce a pulse at the end of each
frame. The width of the pulse will be a minimum of four
hclk
cycles and its polarity can be programmed as shown in Figure
40. The
vsync
level is always synchronized to the active edge
of
pclk
.
Figure 40. vsync in pulse mode
14.5
In odd/even mode the
vsync
signal is used to indicate when
pixel data from an odd and even field is being placed on the dig-
ital video bus
d[11:0]
. The polarity of
vsync
can still be pro-
grammed in this mode as shown in Figure 41
Odd/Even Mode
Figure 41.
vsync
in odd/even Mode
pclk
d[11:0]
pclk
d[11:0]
a) pclk active edge negative
b) pclk active edge positive
invalid pixel data
pclk
d[11:0
]
invalid pixel data
b) hsync programmed to be active low
hsync
Row n
Row n+1
pclk
d[11:0]
a) hsync programmed to be active high (default)
hsyn
c
Row n
Row n+1
pclk
d[11:0
]
hsync
Row n
Row n+1
a) hsync programmed to be active high
pclk
d[11:0]
hsync
Row n
Row n+1
b) hsync programmed to be active low
invalid pixel data
pclk
d[11:0]
invalid pixel data
b) vsync programmed to be active low
vsync
Frame n
Frame n+1
pclk
d[11:0]
a) vsync programmed to be active high
vsync
Frame n
Frame n+1
pclk
d[11:0]
vsync
Frame n
a) vsync programmed to be active high
Frame n+1
pclk
d[11:0]
vsync
Frame n
Frame n+1
b) vsync programmed to be active low (default)
invalid pixel data
pclk
d[11:0]
invalid pixel data
b) vsync programmed to be active low
vsync
Odd Field
Even Field
pclk
d[11:0]
a) vsync programmed to be active high (default)
vsync
Odd Field
Even Field
L
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