參數(shù)資料
型號: LM94CIMT
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: TruTherTM Hardware Monitor with PI Loop Fan Control for Server Management
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO56
封裝: MO-153EE, TSSOP-56
文件頁數(shù): 20/24頁
文件大?。?/td> 693K
代理商: LM94CIMT
AC Electrical Characteristics
The following limits apply for +3.0 V
DC
to +3.6 V
DC
, unless otherwise noted.
Bold face limits apply for T
A
= T
J
= T
MIN
to
T
MAX
of the operating range;
all other limits T
A
= T
J
= 25C unless otherwise noted.
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
FAN RPM-TO-DIGITAL CHARACTERISTICS
Counter Resolution
Number of fan tach pulses count is
based on
Counter Frequency
Accuracy
PWM OUTPUT CHARACTERISTICS
Frequency Tolerances
Duty-Cycle Tolerance
RESET INPUT/OUTPUT CHARACTERISTICS
Output Pulse Width
Upon Power Up
Minimum Input Pulse Width
Reset Output Fall Time
SMBus TIMING CHARACTERISTICS
f
SMBCLK
SMBCLK (Clock) Clock Frequency
14
2
bits
pulses
22.5
kHz
±
6
% (max)
±
6
±
6
% (max)
% (max)
±
2
250
330
10
1
ms (min)
ms (max)
μs (min)
μs (max)
1.6V to 0.4V Logic Levels
10
100
kHz (min)
kHz (max)
t
BUF
SMBus Free Time between Stop and
Start Conditions
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Input Setup Time to SMBCLK
High
Data Output Hold Time after SMBCLK
Low
SMBCLK Low Period
4.7
μs (min)
t
HD;STA
4.0
μs (min)
t
SU;STA
t
SU;STO
t
SU;DAT
4.7
4.0
μs (min)
μs (min)
250
ns (min)
t
HD;DAT
300
1075
4.7
50
4.0
50
1
300
ns (min)
ns (max)
μs (min)
μs (max)
μs (min)
μs (max)
μs (max)
ns (max)
ms
ms (min)
ms (max)
t
LOW
t
HIGH
SMBCLK High Period
t
R
t
F
t
TIMEOUT
Rise Time
Fall Time
Timeout
SMBDAT or SMBCLK low
time required to
reset the Serial Bus
Interface to the Idle State
Time in which a device must be
operational after power-on reset
Capacitance Load on SMBCLK and
SMBDAT
31
25
35
t
POR
V
DD
>
+2.8V
500
ms (max)
C
L
400
pF (max)
L
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