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參數(shù)資料
| 型號： | LM9073T |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Dual High Current Low-Dropout System Regulator |
| 中文描述： | DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PZFM11 |
| 封裝： | POWER, TO-220, 11 PIN |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 718K |
| 代理商： | LM9073T |
Application Information
(Continued)
The Delay Capacitor (C
) controls a time interval during
which the Reset Output remains low after the Main Output
has established normal operating condition. This feature
holds the system in reset for a time to allow all load circuitry
to properly bias before executing functions. This interval is
applied at powerup and following any event that may trigger
the system reset function.
Figure 2 illustrates the delayed reset generator. Two com-
parators continually monitor the Main Output supply. Window
comparators C1 and C2 detect if the Main Supply is below
4.6V (4.1V with Reset Adjust open circuited) or exceeds
5.5V typically. If this is true (at poweron for example) the
control logic turns ON the discharge transistor and holds
C
DELAY
low (at 0.9V). Comparator C4 then outputs a logic
low system Reset signal within 2μS after detecting the out of
regulation condition.
The Delay Capacitor remains discharged until the window
comparator senses that the Main Output is within normal op-
erating range (C1 and C2 outputs are both low). When this
condition is met, the discharge transistor is turned OFF and
C
DELAY
is charged positively by an internal 6μA current
source. The Reset Output will remain low until the delay ca-
pacitor has reached 4V, at which point it will go high and the
system will begin normal operation. This delay time interval
is controlled by the section of C
DELAY
and can be determined
from the following equation:
T
DELAY
= (0.5 x 10
6
) x C
DELAY
A 0.1μF capacitor will produce a typical delay interval of
50mSec.
To ensure a consistent delay time interval, the discharge
transistor is always latched ON by the window comparators,
and can not be switched OFF to start a new delay interval
until C
has been discharged to less than or equal to
0.9V. This sets a fixed starting voltage (0.9V) and ending
voltage (4V) for the charging of the Delay Capacitor.
Watchdog Capacitor (pin 2)
The LM9073 also provides a simple system watchdog timer.
The watchdog timer requires the system controller to issue a
pulse at a regular interval (programmable through the selec-
tion of Cwatchdog) to provide an indication that the system is
properly executing controlling software code. The absence
of a pulse before the watchdog timer comes out could indi-
cate that the system is caught in a infinite loop and the sys-
tem is reset
The watchdog capacitor is held discharged to ground at any
time that the system is reset. When the reset is released the
capacitor quickly charges to 0.9V (with a charging current of
approximately 50μA) then slowly charges positive with a
charging current of 6μA. If this capacitor ever charges up to
4V or more, a system reset is generated.
The watchdog time interval is set by the selection of Cwatch-
dog and can be found from the following equation:
T
WD
= (0.5 x 10
6
) x Cwatchdog
The watchdog timer function can be disabled by grounding
pin 2 or replacing Cwatchdog by a resistor with a value less
than 22k
. With this only the reset generator can reset the
system.
Watchdog Trigger (pin 1)
The Watchdog Trigger input accepts a pulse from the system
controller to refresh the watchdog capacitor and prevent it
from reaching 4V and resetting the system. This positive
pulse must be at least 10μS long and triggers an internal
one-shot pulse. This internal pulse latches ON Qdischarge
Watchdog (figure 2) and discharges Cwatchdog to 0.9V. This
latching action ensures a consistent watchdog timer interval
by not allowing the capacitor to charge positively until it has
been discharged to 0.9V.
As shown in Figure 3, each watchdog trigger input pulse re-
sets the timer capacitor. If the watchdog trigger signal does
not refresh the timer before Cwatchdog reaches 4V, a sys-
tem reset is generated. Once reset, a full reset delay interval
occurs. At the end of this interval the regulator will automati-
cally try to re-start the system by taking reset high. If the sys-
tem does not respond properly by issuing a watchdog trigger
signal in time, the system will once again reset. In this situa-
tion the reset output will continually cycle high (re-starting
the system) for the watchdog time interval and low
(re-setting the system) for the reset delay interval.
Figure 3. Watchdog and Reset Operation
DS101296-18
L
www.national.com
11
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