參數(shù)資料
型號(hào)： LM4560VJD
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 消費(fèi)家電
英文描述： Advanced PCI Audio Accelerator
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 21/54頁(yè)
文件大?。?/td> 380K
代理商： LM4560VJD
3.0 Register Description
(Continued)
10: SB ESP DMA Test Busy
11: SB ESP Command Buffer Full
Bit 10
0: SB ESP Engine at Digital Audio Off State
1: SB ESP Engine at Digital Audio On State
Bit 11
0: SB ESP DMA Command is not valid
1: SB ESP DMA command is valid
Bit 12
0: SB ESP has no ack byte
1: SB ESP has ack byte that needs to be read out
Bit 13
0: SB ESP is not at Direct Recording Mode
1: SB ESP is at Direct Recording Mode
Bit 14
0: SB Mixer Register MX0E.1 is 0
1: SB Mixer Register MX0E.1 is 1
Bit 15
0: AC-97 codec is not ready
1: AC-97 codec is ready
Bit 16
1: OPL3 Bank
0: Key On/Off
Bit 17
1: OPL3 Bank1 Key On/Off
Bit 18
1: SB PRO Mixer Register Update
Bit 19
1: SB16 Mixer Register Update
Bit 20
1: SB Engine Sample Rate Set By Time Constant Most Re-
cently
Bit 21
1: SB Engine Sample Rate Set By Frequency Most Recently
Bit 22
1: SB16 Command Captured Most Recently (Bx or Cx Type
Command Captured)
Bit 23
1: SB PRO Command Captured Most Recently (Non-Bx or
Cx Type Command Captured)
Bit 24
1: SB Mixer Soft-Reset
Bit 26..25
00: SB ESP is at get operator state
01: SB ESP is at get first operand state
11: SB ESP is at get second operand state
10: SB ESP is at get third operand state
Bit 27
1: SB ESP is at special DMA mode
Bit 28
(LREC_IRQ_MASK) Legacy Recording IRQ MASK
0: Generate IRQ when legacy recording block length ex-
pired.
1: Don’t generate IRQ when legacy recording block length
expired.
Bit 29 (MPU_BUF_SEL) MPU401 Output Buffer Select
0: 8-byte
1: 128-byte
Bit 31..30 (Read only) Chip Capability Bits
These two bits are connected to the invert of two bonding op-
tion pads (padt1, padt0). Padt1, padt0 are two input pad with
pull-high resistor which can be bonded to GND.
00 (Default) Full functioned level (64-channel + effect +
AC97 v2.0)
01 Enhanced level (64-channel + effect + AC97 v1.03)
10 Standard level (64-channel + AC97 v1.03)
11Entry level (32-channel + AC97 v1.03)
Bit 24..16 will be cleared after this register is read.
Only one bit of Bit 21 and Bit 20 can be set 1 by implemented
SB ESP Engine at any time.
Only one bit of Bit 23 and Bit 22 can be set 1 by implemented
SB ESP Engine at any time.
3.4.6.2 ASR1 (Legacy Sound Blaster Frequency Read
Back Register)
Address:
AudioBase + 54h
Size:
16 bits
Type:
Read Only
Default:
00h
Bit 15..0 Sample Frequency Set by SB Command 41h or 42h
3.4.6.3 ASR2 (Legacy Sound Blaster Time Constant
Read Back Register)
Address:
AudioBase + 56h
Size:
8 bits
Type:
Read Only
Default:
00h
Bit 7..0 Time Constant Value Set by SB Command 40h
3.4.6.4 ASR3 ( TSAudio Scratch Register)
Address:
AudioBase + 58h
Size:
32 bits
Type:
Read/Write
Default:
00000000h
3.4.6.5 ASR4 (TSAudio Version Control Register)
Address:
AudioBase + 5Ch
Size:
8 bits
Type:
Read Only
Default:
80h
3.4.6.6 ASR5 (SB ESP Version High Byte Control
Register)
Address:
AudioBase + 5Eh
Size:
4 bits
Type:
Read/Write
Default:
4h
3.4.6.7 ASR6 (SB ESP Version Low Byte Control
Register)
Address:
AudioBase + 5Fh
Size:
4 bits
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