參數(shù)資料
型號(hào)： LM4550VH
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 消費(fèi)家電
英文描述： AC ’97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier, Sample Rate Conversion and National 3D Sound
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 X 1.40 MM, LQFP-48
文件頁(yè)數(shù)： 21/25頁(yè)
文件大?。?/td> 507K
代理商： LM4550VH
Application Information
(Continued)
Extended Audio ID Register (28h)
This read only register identifies which AC97 Extended Au-
dio features are supported. The LM4550 features AMAP
(Slot/DAC mappings based on codec ID), VRA (Variable
Rate Audio), and Multiple Codec support. AMAP is indicated
by a "1" in bit 9, VRA is indicated by a "1" in the LSB of
register 28h. The two MSB’s, ID1 and ID0, show the current
codec configuration as connected via external pins 45 and
46. Note that the external logic connection to pins 45 and 46
are inverse in polarity to the internal register setting.
Pin46 (ID1)
NC (not connected)
NC/DV
DD
NC/DV
DD
GND
GND
Pin45 (ID0)
NC (not connected)
NC/DV
DD
GND
NC/DV
DD
GND
Reg 28h ID1
0
0
0
1
1
Reg 28h ID0
0
0
1
0
1
Codec Mode
Primary
Primary
Secondary 1
Secondary 2
Secondary 3
Extended Audio Status/Control Register (2Ah)
This read/write register provides status and control of the
Variable Sample Rate function. Setting the LSB of this reg-
ister to "1" enables Variable Rate Audio (VRA) mode and
allows DAC and ADC sample rates to be programmed via
registers 2Ch and 32h.
BIT
VRA
Function
0 = VRA off (48kHz fixed), 1 = VRA on
Sample Rate Control Registers (2Ch, 32h)
These read/write registers are used to set the sample rate
for the left and right channels of the DAC (2Ch) and the ADC
(32h). When Variable Rate Audio is enabled via bit-0 of
Register 2Ah, the sample rates can be programmed, in 1Hz
increments, to be any value from 4kHz to 48kHz. Below is a
list of the most common sample rates and their correspond-
ing register values.
SR15:SR0
1F40h
2B11h
3E80h
5622h
AC44h
BB80h
Sample Rate (Hz)
8000
11025
16000
22050
44100
48000
Chain-in Control Register (74h)
This register is only needed when using the Chain-in feature.
This feature goes beyond the AC ’97 specification and is not
required for standard AC-Link operation. The two LSBs of
this register default to the codec ID at codec reset. This
default state corresponds to standard AC-Link operation: the
output of codec pin 8 SDATA_IN is the output AC-Link frame
corresponding to the codec.
If the two LSBs are made not equal to the codec’s ID
(register 28h describes codec ID), then the signal present at
pin 48 CHAIN_IN is switched through and output at pin 8
SDATA_IN. In this fashion, secondary codecs can be
chained together by connecting one codec’s SDATA_IN pin
to the next codec’s CHAIN_IN pin. This has the end result of
only requiring a single SDATA_IN pin on the controller chip
instead of the standard one SDATA_IN pin per codec.
The last codec in the serial chain should have its CHAIN_IN
pin connected to digital ground. When writing the software,
care should be taken to avoid any problems that could occur
when the last codec in the chain is set to pass a chain-in
signal when there is none to pass. Different controllers may
handle a stream of all 0s differently and leaving the CHAI-
N_IN pin floating is definitely to be avoided.
Reserved Registers
Do not write to these registers as they are reserved.
AC’97 2.1 Multiple Codec
There can be up to four Codecs on the extended AC-link.
Multiple Codec AC-link implementations must run off a com-
mon BIT_CLK generated by the primary Codec. All four
codecs
will
share
controller
SDATA_OUT, and RESET
#
from the AC’97 Digital Control-
ler. Each device however, requires its own SDATA_IN pin
back to the controller.
ID pins 45 and 46 are internally pulled up to V
. For
example to configure the Codec as a primary the ID pins
could be either left floating or pulled up.
pins
such
as,
SYNC,
L
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21
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參數(shù)描述
LM4550VH WAF 制造商:Texas Instruments 功能描述:
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