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參數(shù)資料
| 型號： | LM27241MTC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Synchronous Buck Regulator Controller for Mobile Systems |
| 中文描述： | SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 3/27頁 |
| 文件大小： | 1336K |
| 代理商： | LM27241MTC |
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Pin Description
(Continued)
tive of the output voltage level. PGOOD must always first be
"high" before it can respond to a proper fault "low" condition.
Under fault assertion, the low-side MOSFET is always
latched ON. This will not happen if regulation has not already
been achieved.
Pin 7, FPWM:
Logic input for selecting either the Forced
PWM (FPWM) Mode or Pulse-skip Mode (SKIP). When the
pin is driven high, the IC operates in the FPWM mode, and
when pulled low or left floating, the SKIP mode is enabled. In
FPWM mode, the lower FET is always ON whenever the
upper FET is OFF (except for a narrow shoot-through pro-
tection deadband). This leads to continuous conduction
mode of operation, which has a fixed frequency and (almost)
fixed duty cycle down to very light loads. But this does
reduce efficiency at light loads. The alternative mode is SKIP
mode. This mode forces the lower MOSFET ON only until
the voltage on the Switch pin is more negative than 2.2mV
(typical). As an example, for a 21m
FET, this translates to
a current threshold of 2.2mV/21m
= 0.1A. Therefore, if the
(instantaneous) inductor current falls below this value, the
lower FET will turn OFF every cycle at this point (when
operated in SKIP mode). This threshold is set by the zero-
cross Comparator in the Block Diagram. Note that if the
inductor current is high enough to be always above this
zero-cross threshold (V
SW_ZERO
, see Electrical Characteris-
tics table), there will be no observable difference between
FPWM and SKIP mode settings (in steady-state). SKIP
mode is clearly a discontinuous mode of operation. How-
ever, in conventional discontinuous mode, the duty cycle
keeps falling (towards zero) as the load decreases. But the
LM27241 does not allow the duty cycle to fall by more than
15% of its original value (at the CCM-DCM boundary). This
forces pulse-skipping, and the average frequency is effec-
tively decreased as the load decreases. This mode of opera-
tion improves efficiency at light loads, but the frequency is
effectively no longer a constant. Note that
a minimum pre-
load of 0.1mA should be maintained on the output to ensure
regulation in SKIP mode.
The resistive divider from output to
ground used to set the output voltage could be designed to
serve as part or all of this required pre-load.
Pin 8, COMP:
Compensation pin. This is also the output of
the error amplifier. The voltage level on this pin is compared
with an internally generated ramp signal to set the duty cycle
for normal regulation. Since the Feedback pin is the inverting
input of the same error amplifier, appropriate control loop
compensation components are placed between this pin and
the Feedback pin. The COMP pin is internally pulled low
during Soft-start so as to limit the duty cycle. Once Soft-start
is completed, the voltage on this pin can take up the value
required to maintain output regulation. An internal voltage
clamp at this pin forms an adaptive duty cycle clamp feature.
This serves to limit the maximum allowable duty cycles and
peak currents under sudden overloads. But at the same time
it has enough headroom to permit an adequate response to
step loads within the normal operating range.
Pin 9, FB:
Feedback pin. This is the inverting input of the
error amplifier. The voltage on this pin under regulation is
nominally at 0.6V. A Power Good window on this pin deter-
mines if the output voltage is within regulation limits (
±
13%).
If the voltage falls outside this window for more than 7μs,
Power Not Good is signaled on the PGOOD pin (Pin 6).
Output over-voltage and under-voltage conditions are also
detected by comparing the voltage on the Feedback pin with
appropriate internal reference voltage levels. If the voltage
exceeds the safe window (
±
30%) for longer than 7μs, a fault
condition is asserted. Then lower FET is latched ON and the
upper FET is latched OFF.
Pin 10, SENSE:
Output voltage sense pin. It is tied directly
to the output rail. The SENSE pin voltage is used together
with the VIN voltage (on Pin 18) to (internally) calculate the
CCM (continuous conduction mode) duty cycle. This calcu-
lation is used by the IC to set the minimum duty cycle in the
SKIP mode to 85% of the CCM value. It is also used to set
the adaptive duty cycle clamp. An internal 20
resistor from
the SENSE pin to ground discharges the output capacitor
gently (Soft-shutdown) whenever Power Not Good is sig-
naled on Pin 6.
Pin 11, ILIM:
Current Limit pin. When the bottom FET is ON,
a 62μA (typical) current flows out of the ILIM pin and into an
external resistor that is connected to the drain of the lower
MOSFET. This current through the resistor creates a voltage
on the ILIM pin. However, the drain voltage of the lower
MOSFET will go more negative as the load current is in-
creased through the R
of the MOSFET. At some value
of instantaneous current, the voltage on this pin will transit
from positive to negative. The point where it is zero is the
current limiting condition and is detected by the Current Limit
Comparator. When a current limit condition has been de-
tected, the next ON-pulse of the upper FET will be omitted.
The lower FET will again be monitored to determine if the
current has fallen below the threshold. If it has, the next
ON-pulse will be permitted. If not, the upper FET will be
turned OFF and will stay so for several cycles if necessary,
until the current returns to normal. Eventually, if the overcur-
rent condition persists, and the upper FET has not been
turned ON, the output will clearly start to fall. Ultimately the
output will fall below the under-voltage threshold, and a fault
condition will be asserted by the IC.
Pin 12, SW:
The Switching node of the buck regulator. Also
serves as the lower rail of the floating driver of the upper
FET.
Pin 13, HDRV:
Gate drive pin for the upper FET. The top
gate driver is interlocked with the bottom gate driver to
prevent shoot-through/cross-conduction.
Pin 14, BOOT:
Bootstrap pin. This is the upper supply rail for
the floating driver of the upper FET. It is bootstrapped by
means of a ceramic capacitor connected to the channel
Switching node. This capacitor is charged up by the IC to a
value of about 5V as derived from the V5 pin (Pin 17).
Pin 15, PGND:
Power Ground pin. This is the return path for
the bottom FET gate drive. The PGND is to be connected on
the PCB to the system ground and also to the Signal ground
(Pin 4) in accordance with the recommended Layout Guide-
lines .
Pin 16, LDRV:
Gate drive pin for the bottom FET (Low-side
drive). The bottom gate driver is interlocked with the top gate
driver to prevent shoot-through/cross-conduction. It is al-
ways latched high when a fault condition is asserted by the
IC.
Pin 17, V5:
Upper rail of the lower FET driver. Also used to
charge up the bootstrap capacitor of the upper FET driver.
This is connected to an external 5V supply. The 5V rail may
be the same as the rail used to provide power to the VDD pin
(Pin 1), but the VDD pin will then require to be well-
decoupled so that it does not interact with the V5 pin. A
low-pass RC filter consisting of a ceramic 0.1μF capacitor
(preferably 0.22μF) and a 10
resistor will suffice as shown
in the Typical Applications circuit.
Pin 18, VIN:
The input to the Buck regulator power stage. It
is also used by the internal ramp generator to implement the
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LM27241MTC/NOPB | 功能描述:IC REG CTRLR BUCK PWM VM 20TSSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:4,000 系列:- PWM 型:電壓模式 輸出數(shù):1 頻率 - 最大:1.5MHz 占空比:66.7% 電源電壓:4.75 V ~ 5.25 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 85°C 封裝/外殼:40-VFQFN 裸露焊盤 包裝:帶卷 (TR) |
| LM27241MTCX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Synchronous Buck Regulator Controller for Mobile Systems |
| LM27241MTCX/NOPB | 功能描述:IC REG CTRLR BUCK PWM VM 20TSSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:100% 電源電壓:8.2 V ~ 30 V 降壓:無 升壓:無 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:0°C ~ 70°C 封裝/外殼:8-DIP（0.300"，7.62mm） 包裝:管件 產(chǎn)品目錄頁面:1316 (CN2011-ZH PDF) |
| LM27243A E WAF | 制造商:Texas Instruments 功能描述: |
| LM2724A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Speed 3A Synchronous MOSFET Driver |
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