參數(shù)資料
型號: LM2720M
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: RES, 10K0 .125W 1% SMT, 0805
中文描述: SWITCHING CONTROLLER, 8700 kHz SWITCHING FREQ-MAX, PDSO24
封裝: PLASTIC, SOIC-24
文件頁數(shù): 5/8頁
文件大?。?/td> 149K
代理商: LM2720M
Pin Description
Pin
1
2
Pin Name
Vcc5V
Divsel
Pin Function
Supply Voltage Input (5V nominal)
Selects Phase Mode. Logic low selects 4 phase. Logic high selects 3 phase. 2 phase
operation is achieved by using 2 outputs in 4 phase mode.
Clock Select: Logic high selects internal clock. Logic low selects external clock.
External Clock Input. Output frequency = Clock Input / No. of Phases. Connect to Vcc5V to
select internal clock.
Connects to external reference resistor. Sets the operating frequency of the internal clock
and the ramp time for the PWM. Reference voltage at this pin is 1.26V.
5-Bit DAC Input (LSB).
5-Bit DAC Input.
5-Bit DAC Input.
5-Bit DAC Input.
5-Bit DAC Input (MSB)
Over-current Comparator. Non-inverting input.
Over-current Comparator. Inverting input.
Compensation Pin. This is the output of the internal transconductance amplifier.
Compensation network should be connected between this pin and feedback ground FBG.
Feedback Input. Normally Kelvin connected to supply output.
Current Limit Flag. Goes to logic low when current limit is activated. When over-current
condition is removed, this pin is weakly pulled up to Vcc5V.
Feedback Ground. This pin should be connected to the ground at the supply output.
Output Enable Pin. Tie to logic high to enable and logic low to disable.
Power Ground Pin.
Phase 2 Output.
Phase 0 Output.
Supply Voltage for FET Drivers DRV0:3.
Phase 1 Output.
Phase 3 Output.
Power Good. This is an open-drain output that goes low (low impedance to ground) when
the output voltage travels out of the threshold window, and resume to open-drain state when
V
OUT
recovers into the 50mV hysteresis window. The power good window threshold, i.e.
±
100mV for 1.3V
V
OUT
1.9V or
±
150mV for 2V
V
OUT
3.5V, is automatically set
according to VID code. Connect a 1nF capacitor to ground to filter out the switching noise
coupling from DRV3 to this pin.
3
4
Clksel
Extclk
5
Rref
6
7
8
9
Vid0
Vid1
Vid2
Vid3
Vid4
OC+
OC
COMP
10
11
12
13
14
15
FB
Bgout
16
17
18
19
20
21
22
23
24
FBG
ENABLE
GND
DRV2
DRV0
Vcc12V
DRV1
DRV3
PWRGD
L
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