參數(shù)資料
型號(hào): LM12L458
廠商: National Semiconductor Corporation
英文描述: 12-Bit Sign Data Acquisition System with Self-Calibration
中文描述: 12位注冊(cè)數(shù)據(jù)采集系統(tǒng)自校準(zhǔn)
文件頁數(shù): 6/36頁
文件大?。?/td> 695K
代理商: LM12L458
Digital Timing Characteristics
The following specifications apply for V
+ = V
+ = 3.3V, t
= t
f
= 3 ns, and C
L
= 100 pF on data I/O, INT and DMARQ lines
unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C. (Notes 6, 7, 8)
Symbol
(See
Figures 10,
11, 12
)
Typical
(Note 10)
Limits
(Note 11)
Unit
(Limit)
Parameter
Conditions
1, 3
CS or Address Valid to ALE Low
Set-Up Time
CS or Address Valid to ALE Low
Hold Time
ALE Pulse Width
RD High to Next ALE High
ALE Low to RD Low
RD Pulse Width
RD High to Next RD or WR Low
ALE Low to WR Low
WR Pulse Width
WR High to Next ALE High
WR High to Next RD or WR Low
Data Valid to WR High Set-Up Time
Data Valid to WR High Hold Time
RD Low to Data Bus Out of TRI-STATE
40
ns (min)
2, 4
20
ns (min)
5
6
7
8
9
10
11
12
13
14
15
16
45
35
20
100
100
20
60
75
140
40
30
10
70
10
110
10
95
20
20
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
ns (min)
ns (min)
30
17
RD High to TRI-STATE
R
L
= 1 k
30
18
RD Low to Data Valid (Access Time)
30
20
21
19
Address Valid or CS Low to RD Low
Address Valid or CS Low to WR Low
Address Invalid
from RD or WR High
INT High from RD Low
10
22
30
10
60
10
60
ns (min)
ns (max)
ns (min)
ns (max)
23
DMARQ Low from RD Low
30
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2:
All voltages are measured with respect to GND, unless otherwise specified.
Note 3:
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
<
GND or V
IN
>
(V
A
+ or V
D
+)), the current at that pin should be limited to 5 mA.
The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current of 5 mA, to simultaneously exceed the power supply volt-
ages.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
(maximum junction temperature),
θ
JA
(package junction
to ambient thermal resistance), and T
(ambient temperature). The maximum allowable power dissipation at any temperature is PD
=(T
Jmax
T
)/
θ
or the num-
ber given in the Absolute Maximum Ratings, whichever is lower. For this device, T
Jmax
= 150C, and the typical thermal resistance (
θ
JA
) of the LM12L454 and
LM12L458 in the V package, when board mounted, is 47C/W.
Note 5:
Human body model, 100 pF discharged through a 1.5 k
resistor.
Note 6:
Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above V
A
+ or 5V below GND
will not damage the LM12L458. However, errors in the A/D conversion can occur if these diodes are forward biased by more than 100 mV. As an example, if V
A
+ is
3.0 V
DC
, full-scale input voltage must be
3.1 V
DC
to ensure accurate conversions.
www.national.com
6
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