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參數(shù)資料
| 型號： | LM1229VEC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | I2C Compatible CMOS TV RGB and Deflection Processor |
| 中文描述： | WAVEFORM GENERATION, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大小： | 969K |
| 代理商： | LM1229VEC |
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Application Information
(Continued)
BLANKING
The pin 18 horizontal flyback input switches at about 2.4V
based on an internal reference.Alarge amplitude input pulse
is more desireable since it reduces the rise time at pin 18.
The component values shown in
Figure 3
have been se-
lected for a horizontal flyback amplitude of 40V peak to peak.
This gives about 2 milliamps peak in the 3.9V zener diode.
The internal blanking pulse is shown in
Figure 4
with its
relationship to the external input.
The pin 62 vertical flyback input requires an AC coupled
waveform. The time constant should be chosen to make a
highpass filter to eliminate the slope of the vertical flyback
waveform during vertical scan. The values in
Figure 5
are for
a vertical flyback amplitude of 45V peak to peak. C
F
may be
needed to prevent horizontal rate noise from causing mul-
tiple triggering of the vertical blanking pulse. It can be as
large as 1000 pF. Care must also be taken to ensure the
voltage at pin 62 does not go below ground or above V
CC
.
CLAMP PULSE
In order for the video processing to operate correctly, there
must be a clamping pulse present on pin 50. The polarity of
this pulse can be selected with bit 3 of the GLOBAL register.
Only about 1V peak to peak is needed to operate the clamp
and it is often desireable to have a 3.3k to 3.9k series
resistor to attenuate the signal to prevent it from coupling
into other signal lines.
DIGITAL OSD OPERATION
The LM1229 is configured for digital OSD operation by set-
ting the DA bit, 0x0B[4], to 0. This is also the power on
default. The On Screen Display must be provided from an
external source. The contrast of the OSD can be controlled
with the OSD_Cont bits, OSD[1:0]. The OSD Enable input
causes the LM1229 output to switch from video to OSD.
Depending on the TRANS bit, 0x0B[3], the OSD background
will be either black or video with contrast setting determined
by the OSD TRANS register, 0x0A[6:0].
Figure 6
shows one
possible OSD timing where the Enable is longer than the
OSD white block itself. In
Figure 7
the transparency bit is 0,
resulting in a black background while the OSD Enable is
active. In
Figure 8
the transparency bit is 1, resulting in a
background of video whose contrast is determined by the
OSD TRANS register. Care should be taken in setting the
OSD TRANS register since it is independent of the
CONTRAST register and therefore it is possible to make the
OSD background contrast higher than that of the surround-
ing video. In normal use as seen in
Figure 8
, the OSD
TRANS register is set to a lower value than the CONTRAST
register. See
Table 2
for the OSD as a function of the TRANS
bit of the OSD register and the OSD Enable input.
20118734
FIGURE 3. Horizontal Flyback
20118735
FIGURE 4. Internal Blank Timing
20118736
FIGURE 5. Vertical Flyback
20118737
FIGURE 6. OSD Timing Example
20118738
FIGURE 7. Opaque OSD Background
20118739
FIGURE 8. Transparent OSD Background
L
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相關(guān)代理商/技術(shù)參數(shù) |
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