參數(shù)資料
型號: LH7A400N0F000B5
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A400N0F000B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT1020-1.html<1<Always Pb-free,;LH7A400N0F076B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 25/65頁
文件大小: 834K
代理商: LH7A400N0F000B5
32-Bit System-on-Chip
LH7A400
Preliminary data sheet
Rev. 01
16 July 2007
25
NXP Semiconductors
The Asynchronous Memory Controller has six main
functions:
Memory bank select
Access sequencing
Wait states generation
Byte lane write control
External bus interface
CompactFlash or PCMCIA interfacing.
Synchronous Memory Controller
The Synchronous memory controller provides a high
speed memory interface to a wide variety of Synchro-
nous memory devices, including SDRAM, Synchro-
nous Flash and Synchronous ROMs.
The key features of the controller are:
LCD DMA port for high bandwidth
Up to four Synchronous Memory banks that can be
independently set up
Special configuration bits for Synchronous ROM
operation
Ability to program Synchronous Flash devices using
write and erase commands
On booting from Synchronous ROM, (and optionally
with Synchronous Flash), a configuration sequence is
performed before releasing the processor from reset
Data is transferred between the controller and the
SDRAM in quad-word bursts. Longer transfers within
the same page are concatenated, forming a seam-
less burst
Programmable for 16- or 32-bit data bus size
Two reset domains are provided to enable SDRAM
contents to be preserved over a ‘soft’ reset
Power saving Synchronous Memory SCKE and
external clock modes provided.
MultiMediaCard (MMC)
The MMC adapter combines all of the requirements
and functions of an MMC host. The adapter supports
the full MMC bus protocol, defined by the MMC Defini-
tion Group’s specification v.2.11. The controller can
also implement the SPI interface to the cards.
INTERFACE DESCRIPTION AND MMC OVERVIEW
The MMC controller uses the three-wire serial data
bus (clock, command, and data) to transfer data to and
from the MMC card, and to configure and acquire status
information from the card’s registers.
MMC bus lines can be divided into three groups:
Power supply: VDD and VSS
Data Transfer: MMCCMD, MMCDATA
Clock: MMCLK.
MULTIMEDIACARD ADAPTER
The MultiMediaCard Adapter implements MultiMedia-
Card specific functions, serves as the bus master for the
MultiMediacard Bus and implements the standard inter-
face to the MultiMediaCard Cards (card initialization,
CRC generation and validation, command/response
transactions, etc.).
Smart Card Interface (SCI)
The SCI (ISO7816) interfaces to an external Smart
Card reader. The SCI can autonomously control data
transfer to and from the smart card. Transmit and
receive data FIFOs are provided to reduce the required
interaction between the CPU core and the peripheral.
SCI FEATURES
Supports asynchronous T0 and T1 transmission
protocols
Supports clock rate conversion factor F = 372, with
bit rate adjustment factors D = 1, 2, or 4 supported
Eight-character-deep buffered Tx and Rx paths
Direct interrupts for Tx and Rx FIFO level monitoring
Interrupt status register
Hardware-initiated card deactivation sequence on
detection of card removal
Software-initiated card deactivation sequence on
transaction complete
Limited support for synchronous Smart Cards via
registered input/output.
PROGRAMMABLE PARAMETERS
Smart Card clock frequency
Communication baud rate
Protocol convention
Card activation/deactivation time
Check for maximum time for first character of
Answer to Reset - ATR reception
Check for maximum duration of ATR character
stream
Check for maximum time of receipt of first character
of data stream
Check for maximum time allowed between characters
Character guard time
Block guard time
Transmit/receive character retry.
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