參數(shù)資料
型號(hào)： LFXP2-40E-6FN484I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： FPGA
中文描述： FPGA, 357 MHz, PBGA484
封裝： 23 X 23 MM, LEAD FREE, FPBGA-484
文件頁(yè)數(shù)： 7/92頁(yè)
文件大?。?/td> 1701K
代理商： LFXP2-40E-6FN484I
2-12
Architecture
Lattice Semiconductor
LatticeXP2 Family Data Sheet
Primary Clock Routing
The clock routing structure in LatticeXP2 devices consists of a network of eight primary clock lines (CLK0 through
CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the
device. All the clock sources are connected to these muxes. Figure 2-9 shows the clock routing for one quadrant.
Each quadrant mux is identical. If desired, any clock can be routed globally.
Figure 2-9. Per Quadrant Primary Clock Selection
Dynamic Clock Select (DCS)
The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent
input clock sources without any glitches or runt pulses. This is achieved irrespective of when the select signal is
toggled. There are two DCS blocks per quadrant; in total, eight DCS blocks per device. The inputs to the DCS block
come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7 (see Figure 2-
Figure 2-10 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed
to other modes. For more information on the DCS, please see TN1126, LatticeXP2 sysCLOCK PLL Design and
Figure 2-10. DCS Waveforms
Secondary Clock/Control Routing
Secondary clocks in the LatticeXP2 devices are region-based resources. The benefit of region-based resources is
the relatively low injection delay and skew within the region, as compared to primary clocks. EBR rows, DSP rows
and a special vertical routing channel bound the secondary clock regions. This special vertical routing channel
aligns with either the left edge of the center DSP block in the DSP row or the center of the DSP row. Figure 2-11
shows this special vertical routing channel and the eight secondary clock regions for the LatticeXP2-40.
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
30:1
29:1
30:1
8 Primary Clocks (CLK0 to CLK7) per Quadrant
DCS
Primary Clock Sources: PLLs + CLKDIVs + PIOs + Routing
CLK0
SEL
DCSOUT
CLK1
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參數(shù)描述
LFXP2-40E-6FN672C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 40KLUTs 540 I/O Inst -on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP2-40E-6FN672I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 40K LUTs 540 I/O Ins on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP240E6IF484C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
LFXP240E6IF484I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
LFXP240E6IF672C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
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