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參數(shù)資料
| 型號： | LFXP2-40E-6FN484I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 中文描述： | FPGA, 357 MHz, PBGA484 |
| 封裝： | 23 X 23 MM, LEAD FREE, FPBGA-484 |
| 文件頁數(shù)： | 27/92頁 |
| 文件大?。?/td> | 1701K |
| 代理商： | LFXP2-40E-6FN484I |
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2-30
Architecture
Lattice Semiconductor
LatticeXP2 Family Data Sheet
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-27 shows the Tristate Register Block with the Output Block
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as D-
type or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in
the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct
register for feeding to the output (D0).
Control Logic Block
The control logic block allows the selection and modification of control signals for use in the PIO block. A clock sig-
nal is selected from general purpose routing, ECLK1, ECLK2 or a DQS signal (from the programmable DQS pin)
and is provided to the input register block. The clock can optionally be inverted.
DDR Memory Support
PICs have additional circuitry to allow implementation of high speed source synchronous and DDR memory inter-
faces.
PICs have registered elements that support DDR memory interfaces. Interfaces on the left and right edges are
designed for DDR memories that support 16 bits of data, whereas interfaces on the top and bottom are designed
for memories that support 18 bits of data. One of every 16 PIOs on the left and right and one of every 18 PIOs on
the top and bottom contain delay elements to facilitate the generation of DQS signals. The DQS signals feed the
DQS buses which span the set of 16 or 18 PIOs. Figure 2-28 and Figure 2-29 show the DQS pin assignments in
each set of PIOs.
The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-
tional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR
data from the memory into input register blocks. For additional information on using DDR memory support please
see TN1138, LatticeXP2 High Speed I/O Interface.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFXP2-40E-6FN672C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 40KLUTs 540 I/O Inst -on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP2-40E-6FN672I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 40K LUTs 540 I/O Ins on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP240E6IF484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
| LFXP240E6IF484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
| LFXP240E6IF672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
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