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參數(shù)資料
| 型號(hào)： | LE28DW8102T-90 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 元件分類： | EEPROM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 338K |
| 代理商： | LE28DW8102T-90 |
8 Megabit FlashBank Memory
LE28DW8102T
3
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.01(2/15/2000) No.xxxx-3/19
The software Sector Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software Data
Protect operation. After the loading cycle, the device enters
into an internally timed Erase cycle.( See Table 3 for specific
codes, Figure 5-3 for the timing waveform, and Figure 14 for a
flowchart.) During the Erase operation, the only valid reads are
Data# Polling and Toggle Bit from the selected bank, other
banks may perform normal read.
Write Operation Status Detection
The LE28DW8102T provides two software means to detect the
completion of a Flash bank Program cycle, in order to optimize
the system Write cycle time. The software detection includes
two status bits : Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The
end of Write Detection mode is enabled after the rising edge of
WE#, which initiates the internal Erase or Program cycle.
The actual completion of the nonvolatile write is a synchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion of the
Write cycle. If this occurs, the system will possibly get an
erroneous result, i.e. valid data may appear to conflict with
either DQ
7
or DQ
6
. In order to prevent spurious device rejec-
tion, if an erroneous result occurs, the software routine should
include a loop to read the accessed location an additional two
(2) times. If both reads are valid, then the device has completed
the Write cycle, otherwise the rejection is valid.
There is no provision to abort an Erase or Program operation,
once initiated. For the SANYO Flash technology, the associ-
ated Erase and Program times are so fast, relative to system
reset times, there is no value in aborting the operation. Note,
reads can always occur from any bank not performing an Erase
or Program operation.
Should the system reset, while a Block or Sector Erase or Word
Program is in progress in the bank where the boot code is
stored, the system must wait for the completion of the operation
before reading that bank. Since the maximum time the system
would have to wait is 25 ms (for a Block Erase), the system ability
to read the boot code would not be affected.
Data# Polling (DQ
7
)
When the LE28DW8102T is in the internal Flash bank Program
cycle, any attempt to read DQ
7
of the last word loaded during
the Flash bank Word Load cycle will receive the complement
of the true data. Once the Write cycle is completed, DQ
7
will
show true data. The device is then ready for the next operation.
(See Figure 6 for the Flash bank Data Polling timing waveforms
and Figure 16 for a flowchart.)
Toggle Bit (DQ
6
)
During the Flash bank internal Write cycle, any consecutive
attempts to read DQ
6
will produce alternating 0's and 1's, i.e.
toggling between 0 and 1. When the Write cycle is completed,
the toggling will stop. The device is then ready for the next
operation. (See Figure 7 for Flash bank Toggle Bit timing
waveforms and Figure 16 for a flowchart.)
Data Protection
The LE28DW8102T provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will not
initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is inhib-
ited when V
DD
is less than 1.5 volts.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high
will inhibit the Write operation. This prevents inadvertent
writes during power-up or power-down.
Software Data Protection (SDP)
The LE28DW8102T provides the JEDEC approved software
data protection scheme as a requirement for initiating a Write,
Erase, or Program operation. With this scheme, any Write
operation requires the inclusion of a series of three word-load
operations to precede the Word Program operation. The three-
word load sequence is used to initiate the Program cycle,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down. The
six-word sequence is required to initiate any Bank, Block, or
Sector Erase operation.
The requirements for JEDEC compliant SDP are in byte format.
The LE28DW8102T is organized by word; therefore, the con-
tents of DQ
8
to DQ
15
are "Don't Care"during any SDP (3-word
or 6-word) command sequence.
During the SDP load command sequence, the SDP load cycle
is suspended when WE# is high. This means a read may occur
to any other bank during the SDP load sequence.
The bank reserve in SDP load sequence is reserved by the bus
cycle of command materialization. If the command sequence
is aborted, e.g., an incorrect address is loaded, or incorrect data
is loaded, the device will return to the Read mode within T
RC
of execution of the load error.
Concurrent Read and Write Operations
The LE28DW8102T provides the unique benefit of being able
to read any bank, while simultaneously erasing, or program-
ming one other bank. This allows data alteration code to be
executed from one bank, while altering the data in another bank.
The next table lists all valid states.
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