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參數(shù)資料
| 型號： | LC80101M |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Special-Purpose Descrambler LSI for Use In VICS Systems.(用于VICS系統(tǒng)的特殊用途密碼器LSI) |
| 中文描述： | 特殊的利用目的解擾器大規(guī)模集成電路在VICS系統(tǒng)。（用于VICS系統(tǒng)的特殊用途密碼器大規(guī)模集成電路） |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 162K |
| 代理商： | LC80101M |
No. 5438-2/9
LC80101M
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Clock low-level time
t
CL
t
CH
t
SU
t
HD
t
EL
t
ES
t
EH
t
DH
CL2
0.7
μs
Clock high-level time
CL2
0.7
μs
Data setup time
CL2, DI2
0.7
μs
Data hold time
CL2, DI2
0.7
μs
CE wait time
CL2, CE2
0.7
μs
CE setup time
CL2, CE2
0.7
μs
CE hold time
CL2, CE2
0.7
μs
Data output time
DO2: Varies with the value of the pull-up resistor used
1
μs
Serial Input and Output
(See the serial data timing figures.)
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input high-level voltage
V
IH
CMOS-compatible Schmitt inputs
0.8 V
DD
V
Input low-level voltage
V
IL
Pull-down resistors: INT-R1, TEST1 to TEST4,
and TESTON
0.2 V
DD
V
Input high-level voltage
V
IH
V
IL
V
OH
V
OL
V
OL
Isd
CMOS-compatible Schmitt inputs:
BACKUP, CE2, CL2, DI1, DI2, and RST2
0.8 V
DD
V
Input low-level voltage
0.2 V
DD
V
Output high-level voltage
I
OH
= –4 mA: CE1, CL1, DO1, INT-R2
I
OL
= 4 mA: CE1, CL1, DO1, INT-R2
I
OL
= 2 mA: DO2
With the BACKUP pin low
Rf = 1 M
, FILCK1 = 3.6 MHz: FILCK1
*
1
INT-R1, TEST1 to 4, TESTON
V
DD
– 2.1
V
Output low-level voltage
0.4
V
Output low-level voltage
0.4
V
Standby current
0.01
10
μA
Input sensitivity
Vck
1.0
V
DD
280
Vp-p
k
mA
Pull-down resistance
Rd
70
140
I
DD
1
I
DD
2
I
DD
3
I
DD
4
Sine wave input: 1 V p-p, V
DD
= 5.0 V
*
2
Sine wave input: 5 V p-p, V
DD
= 5.0 V
*
2
Square wave input: 1 V p-p, V
DD
= 5.0 V
*
2
Square wave input: 5 V p-p, V
DD
= 5.0 V
*
2
6
15
Current drain
2.5
7
mA
5
13
mA
1.5
4
mA
Electrical Characteristics
/Input and Output Levels at Ta = –40 to +85°C, V
DD
= 4.5 to 5.5 V, V
SS
= 0 V
Note 1. Since this LSI operates based on the rising edge of the LC72700E 3.6 MHz output (the FILCK pin), the LC72700E 3.6 MHz output signal must be
input to the FILCK1 pin without inverting the polarity.
2. The current drain varies with the input level and the shape of the clock signal input to the FILCK1 pin. The current drain can be reduced by using
waveforms that are closer to square waves than to sine waves, and by using a signal level that is close to V
DD
. The LC72700E 3.6 MHz output is a
square wave with an output level equal to V
DD
.
Block Diagram
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