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參數(shù)資料
| 型號： | LC72191M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 318K |
| 代理商： | LC72191M |
No. 3985-8/16
LC72191, 72191M, 72191JM
No.
Control block/data
Description
Related data
(1)
(2)
(3)
(4)
Programmable divider
data
D0 to D15
Output port data
O0 to O6
General-purpose counter
initial data
CTEN
Reference frequency
data
R0 to R3
This data sets up the programmable divider.
D0 to D15 is a binary value with D15 as the MSB.
The position of the LSB is changed by DV and SP as listed in the table below.
* don’t care
When D4 is the LSB, bits D0 to D3 are ignored.
Data that determines the states of the output ports OUT0 to OUT6. O0 determines the
OUT0 pin output. However, note that when O0 is 0, OUT0 will output a high level, and when O0
is 1, OUT0 will output a low level. O1 to O6 function in the same manner.
These can be used for a wide range of purposes, including, for example, band switching
signals.
When the TB bit is set to 1, the O0 data is ignored and the OUT0 pin outputs an 8 Hz clock
time base signal.
Since the output port states are undefined when power is first applied, transfer the control data
quickly.
Data that determines the operation of the general-purpose counter. When CTEN is 0, the 20-bit
binary counter (the general-purpose counter) is reset and the HCTR and LCTR pins are pulled
down to ground. When CTEN is set to 1, the general-purpose counter reset state is cleared and
the counter operates according to the SC bit (the general-purpose selection data). In this state,
the general-purpose counter will count either the HCTR or LCTR input signal.
Since the general-purpose counter is reset by setting CTEN to 0, the result of a count operation
must be sent to the controller while CTEN is still 1.
Data that selects one of the ten LC72191 reference frequencies or sets the LC72191 to
backup mode in which PLL operation is disabled.
Note: * PLL inhibit (backup mode)
The programmable divider block is turned off, both the FMIN and AMIN pins are pulled
down to ground, and the charge pump outputs go to the floating state.
DV
SP
TB
SC
SF
GT
DV
SP
LSB
Divisor setting
Actual divisor
1
*
D0
256 to 65536
Twice the set value
01
D0
256 to 65536
The set value
00
D4
4 to 4096
The set value
R0
R1
R2
R3
Reference frequency (kHz)
00
0
100
00
0
1
50
00
1
0
25
00
1
25
01
00
12.5
01
6.25
01
10
3.125
01
11
3.125
10
0
10
0
1
9
10
1
0
5
10
1
11
0
11
0
1
PLL inhibit state*
11
1
0
11
1
Continued on next page.
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