參數(shù)資料
型號: LC66354C
廠商: Sanyo Electric Co.,Ltd.
英文描述: Quadruple 2-Input Positive-AND Gates 14-TSSOP -40 to 85
中文描述: 四位單片機與4,6微控制器和8 KB的片上ROM
文件頁數(shù): 9/21頁
文件大?。?/td> 140K
代理商: LC66354C
Allowable Operating Ranges
at Ta = –30 to +70°C, V
SS
= 0 V, V
DD
= 2.5 to 5.5 V, unless otherwise specified.
Note: 1. Applies to pins with open-drain specifications. However, V
IH
2 applies to the P33/HOLD pin.
When ports P2, P3, and P6 have CMOS output specifications they cannot be used as input pins.
2. Applies to pins with open-drain specifications.
3. When RE is used as a three-value input, V
IH
4, V
IM
, and V
IL
4 apply. When the ports PC pins have CMOS output specifications they cannot be used
as input pins.
No. 5484-9/21
LC66354C, 66356C, 66358C
Parameter
Symbol
Conditions
min
typ
max
Unit
Note
Operating supply voltage
V
DD
V
DD
H
V
DD
: 0.92 Tcyc 10 μs
V
DD
: During hold mode
P2, P3 (except for the P33/HOLD pin), P4, P5,
and P6: N-channel output transistor off
2.5
5.5
V
Memory retention supply voltage
1.8
5.5
V
V
IH
1
0.8 V
DD
+13.5
V
1
V
IH
2
P33/HOLD, RES, OSC1:
N-channel output transistor off
0.8 V
DD
V
DD
V
2
Input high-level voltage
V
IH
3
P0, P1, PC, PD, PE:
N-channel output transistor off
0.8 V
DD
V
DD
V
3
V
IH
4
V
IM
PE: With 3-value input used, V
DD
= 3.0 to 5.5 V
PE: With 3-value input used, V
DD
= 3.0 to 5.5 V
PD0, PC2: When the comparator input is used,
V
DD
= 3.0 to 5.5 V
PD1, PD2, PD3, PC3: When the comparator
input is used, V
DD
= 3.0 to 5.5 V
P2, P3 (except for the P33/HOLD pin), P5, P6,
RES, and OSC1: N-channel output transistor off
0.8 V
DD
0.4 V
DD
V
DD
V
Mid-level input voltage
0.6 V
DD
V
V
CMM
1
1.5
V
DD
V
Common-mode input
voltage range
V
CMM
2
V
SS
V
DD
– 1.5
V
V
IL
1
0.2 V
DD
V
2
Input low-level voltage
V
IL
2
P33/HOLD: V
DD
= 1.8 to 5.5 V
P0, P1, P4, PC, PD, PE, TEST:
N-channel output transistor off
0.2 V
DD
V
V
IL
3
V
SS
0.2 V
DD
V
3
V
IL
4
fop
(Tcyc)
PE: With 3-value input used, V
DD
= 3.0 to 5.5 V
V
SS
0.4
(10)
0.2 V
DD
4.35
(0.92)
V
Operating frequency
(instruction cycle time)
MHz
(μs)
[External clock input conditions]
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Frequency
f
ext
0.4
4.35
MHz
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Pulse width
t
extH
, t
extL
100
ns
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Rise and fall times
t
extR
, t
extF
30
ns
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