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參數(shù)資料
| 型號： | LC66354C |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Quadruple 2-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| 中文描述： | 四位單片機(jī)與4,6微控制器和8 KB的片上ROM |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 140K |
| 代理商： | LC66354C |
Continued from preceding page.
No. 5484-16/21
LC66354C, 66356C, 66358C
Instruction code
Affected
status
bits
Mnemonic
Operation
Description
Note
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
[Load and store instructions]
Load the contents of M (reg)
into AC. (The reg is either HL
or XY.) Then increment the
contents of either DP
L
or DP
Y
. ZF
The relationship between t
0
and reg is the same as that
for the LA reg instruction.
ZF is set
according to the
result of
incrementing
DP
L
or DP
Y
.
Load AC from M (reg)
then increment reg
AC
←
[M (reg)]
DP
L
←
(DP
L
) + 1
or DP
Y
←
(DP
Y
) + 1
LA reg, I
0 1 0 0
1 0 t
0
1
1
2
Load the contents of M (reg)
into AC. (The reg is either HL
or XY.) Then decrement the
contents of either DP
L
or DP
Y
. ZF
The relationship between t
0
and reg is the same as that
for the LA reg instruction.
ZF is set
according to the
result of
decrementing
DP
L
or DP
Y
.
LA reg, DLoad AC from M (reg)
AC
←
[M (reg)]
DP
L
←
(DP
L
) – 1
or DP
Y
←
(DP
Y
) – 1
0 1 0 1
1 0 t
0
1
1
2
Exchange the contents of
M (reg) and AC.
The reg is either HL or XY
depending on t
0
.
Exchange AC with
M (reg)
XA reg
0 1 0 0
1 1 t
0
0
1
1
(AC)
[M (reg)]
Exchange the contents of
M (reg) and AC. (The reg is
either HL or XY.) Then
increment the contents of
either DP
L
or DP
Y
. The
relationship between t
0
and
reg is the same as that for
the XA reg instruction.
ZF is set
according to the
result of
incrementing
DP
L
or DP
Y
.
Exchange AC with
(AC)
[M (reg)]
DP
L
←
(DP
) + 1
or DP
Y
←
(DP
Y
) + 1
XA reg, I M (reg) then
increment reg
0 1 0 0
1 1 t
0
1
1
2
ZF
Exchange the contents of
M (reg) and AC. (The reg is
either HL or XY.) Then
decrement the contents of
either DP
L
or DP
Y
. The
relationship between t
0
and
reg is the same as that for
the XA reg instruction.
ZF is set
according to the
result of
decrementing
DP
L
or DP
Y
.
Exchange AC with
(AC)
[M (reg)]
DP
L
←
(DP
) – 1
or DP
Y
←
(DP
Y
) – 1
XA reg, D M (reg) then
decrement reg
0 1 0 1
1 1 t
0
1
1
2
ZF
XADR i8
Exchange AC with
M direct
1 1 0 0
I
7
I
6
I
5
I
4
1 1 0 0
I
7
I
6
I
5
I
4
1 0 0 0
I
3
I
2
I
1
I
0
0 1 1 0
I
3
I
2
I
1
I
0
2
2
(AC)
[M (i8)]
Exchange the contents of AC
and M (i8).
LEAI i8
Load E & AC with
immediate data
2
2
E
←
I
7
I
6
I
5
I
4
AC
←
I
3
I
2
I
1
I
0
Load the immediate data i8
into E, AC.
Load into E, AC the ROM data
at the location determined by
replacing the lower 8 bits of
the PC with E, AC.
RTBL
Read table data from
program ROM
0 1 0 1
1 0 1 0
1
2
E, AC
←
[ROM (PCh, E, AC)]
Output from ports 4 and 5 the
ROM data at the location
determined by replacing the
lower 8 bits of the PC with
E, AC.
Read table data from
program ROM then
output to P4, 5
Port 4, 5
←
[ROM (PCh, E, AC)]
RTBLP
0 1 0 1
1 0 0 0
1
2
[Data pointer manipulation instructions]
Load DP
H
with zero
and DP
L
with
immediate data
respectively
LDZ i4
0 1 1 0
I
3
I
2
I
1
I
0
1
1
DP
H
←
0
DPL
←
I
3
I
2
I
1
I
0
Load zero into DP
H
and the
immediate data i4 into DP
L
.
LHI i4
Load DP
H
with
immediate data
1 1 0 0
0 0 0 0
1 1 1 1
I
3
I
2
I
1
I
0
1 1 1 1
I
3
I
2
I
1
I
0
0 0 0 0
I
3
I
2
I
1
I
0
0 0 0 0
I
3
I
2
I
1
I
0
2
2
DP
H
←
I
3
I
2
I
1
I
0
Load the immediate data i4
into DP
H
.
Load the immediate data i4
into DP
L
.
Load the immediate data into
DL
H
, DP
L
.
Load the immediate data into
DL
X
, DP
Y
.
LLI i4
Load DP
L
with
immediate data
1 1 0 0
0 0 0 1
2
2
DP
L
←
I
3
I
2
I
1
I
0
LHLI i8
Load DP
H
, DP
L
with
immediate data
1 1 0 0
I
7
I
6
I
5
I
4
1 1 0 0
I
7
I
6
I
5
I
4
2
2
DP
H
←
I
7
I
6
I
5
I
4
DP
L
←
I
3
I
2
I
1
I
0
DP
X
←
I
7
I
6
I
5
I
4
DP
Y
←
I
3
I
2
I
1
I
0
LXYI i8
Load DP
X
, DP
Y
with
immediate data
2
2
N
b
N
c
reg
T
0
0
1
HL
XY
Continued on next page.
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