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No. 5487-25/27
LC66P2316
Continued on next page.
Instruction code
Affected
status
bits
Mnemonic
Operation
Description
Note
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
[Branch instructions]
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if (CF) = 1
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if (CF) = 0
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if (ZF) = 1
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if (ZF) = 0
Branch to the location in the
same page specified by P
7
to
P
0
if CF is one.
BC addr
Branch on CF
1 1 0 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
1 1 0 0
2
2
Branch to the location in the
same page specified by P
7
to
P
0
if CF is zero.
BNC
addr
Branch on no CF
1 0 0 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
1 1 0 0
2
2
Branch to the location in the
same page specified by P
7
to
P
0
if ZF is one.
BZ addr
Branch on ZF
1 1 0 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
1 1 0 1
2
2
Branch to the location in the
same page specified by P
7
to
P
0
if ZF is zero.
BNZ
addr
Branch on no ZF
1 0 0 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
1 1 0 1
2
2
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if (Fn) = 1
Branch to the location in the
same page specified by P
0
to
P
7
if the flag (of the 16 user
flags) specified by n
3
n
2
n
1
n
0
is one.
BFn4
addr
1 1 1 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
n
3
n
2
n
1
n
0
Branch on flag bit
2
2
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if (Fn) = 0
Branch to the location in the
same page specified by P
0
to
P
7
if the flag (of the 16 user
flags) specified by n
3
n
2
n
1
n
0
is zero.
BNFn4
addr
1 0 1 1
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
n
3
n
2
n
1
n
0
Branch on no flag bit
2
2
[I/O instructions]
IP0
Input port 0 to AC
0 0 1 0
0 0 0 0
1
1
AC
←
(P0)
Input the contents of port
0 to AC.
ZF
IP
Input port to AC
0 0 1 0
0 1 1 0
1
1
AC
←
[P (DP
L
)]
Input the contents of port
P (DP
L
) to AC.
Input the contents of port
P (DP
L
) to M (HL).
Input the contents of
P (i4) to AC.
ZF
IPM
Input port to M
0 0 0 1
1 0 0 1
1
1
M (HL)
←
[P (DP
L
)]
IPDR i4
Input port to
AC direct
1 1 0 0
0 1 1 0
1 1 1 1
I
3
I
2
I
1
I
0
2
2
AC
←
[P (i4)]
ZF
Input port 4, 5 to
E, AC respectively
1 1 0 0
1 1 0 1
1 1 1 1
0 1 0 0
E
←
[P (4)]
AC
←
[P (5)]
Input the contents of ports
P (4) and P (5) to E and AC
respectively.
IP45
2
2
OP
Output AC to port
0 0 1 0
0 1 0 1
1
1
P (DP
L
)
←
(AC)
Output the contents of AC to
port P (DP
L
).
Output the contents of M (HL)
to port P (DP
L
).
Output the contents of AC
to P (i4).
OPM
Output M to port
0 0 0 1
1 0 1 0
1
1
P (DP
L
)
←
[M (HL)]
OPDR i4
Output AC to
port direct
1 1 0 0
0 1 1 1
1 1 1 1
I
3
I
2
I
1
I
0
2
2
P (i4)
←
(AC)
Output E, AC to port
4, 5 respectively
1 1 0 0
1 1 0 1
1 1 1 1
0 1 0 1
P (4)
←
(E)
P (5)
←
(AC)
Output the contents of E and
AC to ports P (4) and P (5)
respectively.
OP45
2
2
Set to one the bit in port
P (DP
L
) specified by the
immediate data t
1
t
0
.
Clear to zero the bit in port
P (DP
L
) specified by the
immediate data t
1
t
0
.
Take the logical AND of P (P
3
to P
0
) and the immediate data
I
3
I
2
I
1
I
0
and output the result
to P (P
3
to P
0
).
Take the logical OR of P (P
3
to P
0
) and the immediate data ZF
I
3
I
2
I
1
I
0
and output the result
to P (P
3
to P
0
).
SPB t2
Set port bit
0 0 0 0
1 0 t
1
t
0
1
1
[P (DP
L
), t2]
←
1
RPB t2
Reset port bit
0 0 1 0
1 0 t
1
t
0
1
1
[P (DP
L
), t2]
←
0
ZF
And port with
immediate data then
output
P (P
3
to P
0
)
←
[P (P
3
to P
0
)]
I
3
to I
0
ANDPDR
i4, p4
1 1 0 0
I
3
I
2
I
1
I
0
0 1 0 1
P
3
P
2
P
1
P
0
2
2
ZF
Or port with
immediate data then
output
P (P
3
to P
0
)
←
[P (P
3
to P
0
)]
I
3
to I
0
ORPDR
i4, p4
1 1 0 0
I
3
I
2
I
1
I
0
0 1 0 0
P
3
P
2
P
1
P
0
2
2
N
b
N
c