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參數(shù)資料
| 型號(hào)： | LC66354B |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Quadruple 2-Input Positive-AND Gates 14-SO -40 to 85 |
| 中文描述： | 四位單片機(jī)與16 KB的片上微控制器檢察官辦公室胎膜早破 |
| 文件頁(yè)數(shù)： | 14/27頁(yè) |
| 文件大小： | 176K |
| 代理商： | LC66354B |
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Allowable Operating Ranges
at Ta = –30 to +70°C, V
SS
= 0 V, V
DD
= 4.0 to 5.5 V, unless otherwise specified.
Note: 1. Applies to pins with open-drain specifications. However, V
IH
2 applies to the P33/HOLD pin.
When ports P2, P3, and P6 have CMOS output specifications they cannot be used as input pins.
2. PC port pins with CMOS output specifications cannot be used as input pins.
Contact your Sanyo representative for the allowable operating ranges for P4 and PD when the inverter array is used.
No. 5487-14/27
LC66P2316
Parameter
Symbol
Conditions
min
typ
max
Unit
Note
Operating supply voltage
V
DD
V
DD
H
V
DD
V
DD
: During hold mode
P2, P3 (except for the P33/HOLD pin),
P61, and P63: N-channel output transistor off
4.0
5.5
V
Memory retention supply voltage
1.8
5.5
V
V
IH
1
0.8 V
DD
10.0
V
1
Input high-level voltage
V
IH
2
P33/HOLD, RES, OSC1:
N-channel output transistor off
0.8 V
DD
V
DD
V
V
IH
3
P0, P1, P4, P5, PC, PD, PE:
N-channel output transistor off
0.8 V
DD
V
DD
V
2
V
IL
1
P2, P3 (except for the P33/HOLD pin), P6,
RES, and OSC1: N-channel output transistor off
V
SS
0.2 V
DD
V
1
Input low-level voltage
V
IL
2
P33/HOLD: V
DD
= 1.8 to 5.5 V
P0, P1, P4, P5, PC, PD, PE, TEST:
N-channel output transistor off
V
SS
0.2 V
DD
V
V
IL
3
V
SS
0.2 V
DD
V
2
Operating frequency
(instruction cycle time)
fop
(Tcyc)
0.4
(10)
4.20
(0.95)
MHz
(μs)
[External clock input conditions]
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Frequency
f
ext
0.4
4.20
MHz
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Pulse width
t
extH
, t
extL
100
ns
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Rise and fall times
t
extR
, t
extF
30
ns
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