VCCO2 鈥斺€� 鈥� 85 V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� LC51024VG-12F676I
寤犲晢锛� Lattice Semiconductor Corporation
鏂囦欢闋佹暩(sh霉)锛� 61/99闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC XPLD 1024MC 12NS 676FPBGA
妯欐簴鍖呰锛� 27
绯诲垪锛� ispMACH™ 5000VG
鍙法绋嬮鍨嬶細 绯荤当(t菕ng)鍏у彲绶ㄧ▼
鏈€澶у欢閬叉檪闁� tpd(1)锛� 12.0ns
闆诲闆绘簮 - 鍏ч儴锛� 3 V ~ 3.6 V
閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩細 32
瀹忓柈鍏冩暩(sh霉)锛� 1024
杓稿叆/杓稿嚭鏁�(sh霉)锛� 384
宸ヤ綔婧害锛� -40°C ~ 105°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 676-BBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 676-FPBGA锛�31x31锛�
鍖呰锛� 鎵樼洡
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
60
鈥斺€�
VCCO2
鈥斺€�
鈥�
85
VCCO2
2
29N
E10
F5
H5
E11
86
M10
U12
鈥�
GND (Bank 2)
鈥�
87
GND (Bank 2) GND (Bank 2)
2
30P
E12
F6
H6
E13
88
M11
AB13
2
30N
E16
F7
H7
E17
89
T13
Y13
2
31P
E18
鈥�
E19
90
P11
V13
2
31N
E20/VREF2
鈥斺€�
E21
91
T14
W13
2
32P
E22
F8
H8
E23
92
R12
V14
2
32N
E24
F9
H9
E25
93
R13
W14
2
33P
E26
F10
H10
E27
94
N11
Y14
2
33N
E28
F11
H11
E29
95
T15
AB14
2
34P
F0
F12
H12
F1
96
R14
AB15
2
34N
F2
F13
H13
F3
97
N12
AA15
2
35P
F4
F14
H14
F5
98
P12
U13
鈥斺€�
VCCO2
鈥斺€�
鈥�
VCCO2
2
35N
F6
F15
H15
F7
99
R15
U14
鈥�
GND (Bank 2)
鈥�
GND (Bank 2) GND (Bank 2)
2
36P
F8
E0
鈥�
F9
鈥�
W15
2
36N
F10
E2
鈥�
F11
鈥�
W16
2
37P
F12
E4
鈥�
F13
鈥�
Y16
2
37N
F16
E6
鈥�
F17
鈥�
AA16
2
38P
F18
E8
鈥�
F19
鈥�
AB16
2
38N
F20
E10
鈥�
F21
鈥�
AA17
2
39P
F22
E12
鈥�
F23
鈥�
Y17
2
39N
F24
E16
鈥�
F25
鈥�
AA18
2
40P
F26
E20
鈥�
F27
鈥�
W17
2
40N
F28
E22
鈥�
F29
鈥�
W18
2
41P
G0
鈥�
G1
鈥�
V15
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VCCO2
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100
VCCO2
2
41N
G2
鈥�
G3
鈥�
U15
鈥�
GND (Bank 2)
鈥�
101
GND (Bank 2) GND (Bank 2)
2
42P
G4
鈥�
G5
102
P13
Y18
2
42N
G6
鈥�
G7
103
P15
V17
2
43P
G8
鈥�
G9
鈥�
M13
V16
2
43N
G10
鈥�
G11
鈥�
P14
U16
2
44P
G12
鈥�
G13
鈥�
AB18
2
44N
G14
鈥�
G15
鈥�
AB19
2
45P
G16
鈥�
G17
鈥�
U18
2
45N
G18
鈥�
G19
鈥�
T17
2
46P
G20
鈥�
G21
104
R16
AB20
2
46N
G22
鈥�
G23
105
P16
AA20
2
47P
G24
鈥�
G25
106
N15
Y19
鈥斺€�
VCCO2
鈥�
107
VCCO2
ispXPLD 5512MX Logic Signal Connections (Continued)
sysIO
Bank
LVDS
Pair
Primary Macrocell/
Function
Alternate Outputs
Alternate
Input
208 PQFP
Pin Number
256 fpBGA
Ball Number
484 fpBGA
Ball Number
Macrocell 1 Macrocell 2
SELECT
DEVICES
DISCONTINUED
鐩搁棞PDF璩囨枡
PDF鎻忚堪
VI-24K-CY-F2 CONVERTER MOD DC/DC 40V 50W
VI-2TT-CY-F1 CONVERTER MOD DC/DC 6.5V 50W
TAJS334K035RNJ CAP TANT 0.33UF 35V 10% 1206
VI-2T0-CY-F3 CONVERTER MOD DC/DC 5V 50W
NCP1031DR2 IC CTRLR PWM OTP OVD HV 8SOIC
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
LC51024VG-5F484C 鍔熻兘鎻忚堪:CPLD - 寰╅洔鍙法绋嬮倧杓櫒浠� PROGRAM EXPANDED LOG RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜椤炲瀷:EEPROM 澶ч浕姹犳暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅傞枔:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100
LC51024VG-5F676C 鍔熻兘鎻忚堪:CPLD - 寰╅洔鍙法绋嬮倧杓櫒浠� PROGRAM EXPANDED LOG RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜椤炲瀷:EEPROM 澶ч浕姹犳暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅傞枔:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100
LC51024VG75F484C 鍒堕€犲晢:Lattice Semiconductor Corporation 鍔熻兘鎻忚堪:
LC51024VG-75F484C 鍔熻兘鎻忚堪:CPLD - 寰╅洔鍙法绋嬮倧杓櫒浠� PROGRAM EXPANDED LOG RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜椤炲瀷:EEPROM 澶ч浕姹犳暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅傞枔:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100
LC51024VG-75F484I 鍔熻兘鎻忚堪:CPLD - 寰╅洔鍙法绋嬮倧杓櫒浠� PROGRAM EXPANDED LOG RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜椤炲瀷:EEPROM 澶ч浕姹犳暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅傞枔:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100