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參數(shù)資料
| 型號： | LC4101C |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | LCD Dot Matrix Segment Driver for STN Displays |
| 中文描述： | 液晶點陣段驅(qū)動STN彩屏 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 86K |
| 代理商： | LC4101C |
Allowable Operating Ranges
at Ta = –20 to +75°C, standard V
SS
, V
EEn
= V
EE1
or V
EE2
, V
SSn
= V
SS1
or V
SS2
Note: 1. The voltages V
0
, V
2
, V
3
, and V
5
must obey the relationships V
EEn
≥
V
0
≥
V
2
≥
V
EE
– 7, and 7
≥
V
3
≥
V
5
≥
V
SSn
. (Unit: V)
2. When turning on the power supplies, first turn on the logic system power supply and then turn on the high-voltage system power supply;
alternatively, turn both on at the same time.
When turning off the power supplies, first turn off the high-voltage system power supply and then turn off the logic system power supply;
alternatively, turn both off at the same time.
No. 5280-2/9
LC4101C
Parameter
Symbol
Conditions
min
typ
max
Unit
V
DD
V
EEn
V
SSn
3.0
5.5
V
Supply voltage
20
36
V
0
V
Input high-level voltage
V
IH
D0 to D7, CP, L/R, BS, DF, TEST, DISP,
EIO1, EIO2, LOAD
0.8 V
DD
V
DD
V
Input low-level voltage
V
IL
D0 to D7, CP, L/R, BS, DF, TEST, DISP,
EIO1, EIO2, LOAD
0
0.2 V
DD
V
V
0
, V
2
V
3
V
5
f
cp
V
0
, V
2
V
3
V
5
CP
V
EEn
– 7
V
EEn
V
Input voltage
0
V
SSn
+ 7
V
0
V
CP clock frequency
12
MHz
High-level load
pulse width
t
w (ldh)
LOAD
50
ns
High-level clock
pulse width
t
w (cph)
CP
28
ns
Low-level clock
pulse width
t
w (cpl)
CP
28
ns
V
DD
=
5 V ± 10%
Load clock frequency
f
load
t
su (ld)
t
ho (ld)
t
su (cp)
t
ho (cp)
t
su (ei)
t
r
t
f
f
cp
LOAD
1
MHz
LOAD/CP setup time
LOAD, CP
30
ns
LOAD/CP hold time
LOAD, CP
200
ns
DATA/CP setup time
CP, D0 to D7
28
ns
DATA/CP hold time
CP, D0 to D7
20
ns
EIO input setup time
CP, EIO1, EIO2
30
ns
Clock rise time
LOAD, CP
50
ns
Clock fall time
LOAD, CP
50
ns
CP clock frequency
CP
6.5
MHz
High-level load
pulse width
t
w (ldh)
LOAD
50
ns
High-level clock
pulse width
t
w (cph)
CP
40
ns
Low-level clock
pulse width
t
w (cpl)
CP
40
ns
V
DD
=
3 to 4.5 V
Load clock frequency
f
load
t
su (ld)
t
ho (ld)
t
su (cp)
t
ho (cp)
t
su (ei)
t
r
t
f
LOAD
200
kHz
LOAD/CP setup time
LOAD, CP
35
ns
LOAD/CP hold time
LOAD, CP
350
ns
DATA/CP setup time
CP, D0 to D7
50
ns
DATA/CP hold time
CP, D0 to D7
50
ns
EIO input setup time
CP, EIO1, EIO2
45
ns
Clock rise time
LOAD, CP
50
ns
Clock fall time
LOAD, CP
50
ns
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